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8134m?avr?08/2013 features ? high-performance, low-power atmel ? avr ? xmega ? 8/16-bit microcontroller ? nonvolatile program and data memories ? 32k - 384kbytes of in-system self-programmable flash ? 4k - 8kbytes boot section ? 2k - 4kbytes eeprom ? 4k - 16kbytes internal sram ? peripheral features ? four-channel event system ? five 16-bit timer/counters ? four timer/counters with four output compare or input capture channels ? one timer/counter with two output compare or input capture channels ? high resolution extension on two timer/counters ? advanced waveform extension (awex) on one timer/counter ? three usarts with irda support for one usart ? two two-wire interfaces with dual address match (i 2 c and smbus compatible) ? two serial peripheral interfaces (spis) ? crc-16 (crc-ccitt) and crc-32 (ieee ? 802.3) generator ? 16-bit real time counter (r tc) with separate oscillator ? one sixteen-channel, 12-bit, 300ksps analog to digital converter ? two analog comparators with window compare function, and current sources ? external interrupts on all general purpose i/o pins ? programmable watchdog timer with separate on-chip ultra low power oscillator ? atmel qtouch ? library support ? capacitive touch buttons, sliders and wheels ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll and prescaler ? programmable multilevel interrupt controller ? five sleep modes ? programming and debug interface ? pdi (program and debug interface) ? i/o and packages ? 50 programmable i/o pins ? 64-lead tqfp ? 64-pad qfn ? operating voltage ? 1.6 ? 3.6v ? operating frequency ? 0 ? 12mhz from 1.6v ? 0 ? 32mhz from 2.7v 8/16-bit atmel avr xmega d3 microcontroller atxmega32d3* / atxmega64d3 / atxmega128d3 / atxmega192d3 / atxmega256d3 / atxmega384d3* *preliminary
2 xmega d3 [datasheet] 8134m?avr?08/2013 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restri ction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?packaging information? on page 61 . 4. tape and reel. ordering code flash [bytes] eeprom [bytes] sram [bytes] speed [mhz] power supply package (1)(2)(3) temp. atxmega32d3-au 32k + 4k 2k 4k 32 1.6 - 3.6v 64a -40 ? c - 85 ? c atxmega32d3-aur (4) 32k + 4k 2k 4k atxmega64d3-au 64k + 4k 2k 4k atxmega64d3-aur (4) 64k + 4k 2k 4k atxmega128d3-au 128k + 8k 2k 8k atxmega128d3-aur (4) 128k + 8k 2k 8k atxmega192d3-au 192k + 8k 2k 16k atxmega192d3-aur (4) 192k + 8k 2k 16k atxmega256d3-au 256k + 8k 4k 16k atxmega256d3-aur (4) 256k + 8k 4k 16k atxmega384d3-au 384k + 8k 4k 32k atxmega384d3-aur (4) 384k + 8k 4k 32k atxmega32d3-mh 32k + 4k 2k 4k 64m atxmega32d3-mhr (4) 32k + 4k 2k 4k atxmega64d3-mh 64k + 4k 2k 4k atxmega64d3-mhr (4) 64k + 4k 2k 4k atxmega128d3-mh 128k + 8k 2k 8k atxmega128d3-mhr (4) 128k + 8k 2k 8k atxmega192d3-mh 192k + 8k 2k 16k atxmega192d3-mhr (4) 192k + 8k 2k 16k atxmega256d3-mh 256k + 8k 4k 16k atxmega256d3-mhr (4) 256k + 8k 4k 16k atxmega384d3-mh 384k + 8k 4k 32k atxmega384d3-mhr (4) 384k + 8k 4k 32k package type 64a 64-lead, 14 * 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) 64m 64-pad, 9 * 9 * 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (qfn)
3 xmega d3 [datasheet] 8134m?avr?08/2013 typical applications industrial control climate control low power battery applications factory automation rf and zigbee ? power tools building control motor control hvac board control sensor control utility metering white goods optical medical applications
4 xmega d3 [datasheet] 8134m?avr?08/2013 2. pinout/block diagram figure 2-1. block diagram and pinout. notes: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 49 . 2. the large center pad underneath the qfn/mlf package should be soldered to ground on the board to ensure good mechanical stability. 1 2 3 4 64 63 62 61 60 59 58 vcc 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gnd gnd vcc avcc gnd pb0 pb1 pb3 pb2 pb7 pb5 pb4 pb6 pa7 pa6 pa0 pa1 pa2 pa3 pa4 pa5 _reset/pdi pdi pr0 pr1 vcc gnd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 vcc gnd pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 vcc gnd power supervision port a event routing network sram flash adc ac0:1 ocd port e port d prog/debug interface eeprom port c tc0:1 event system controller watchdog timer internal oscillators osc/clk control real time counter interrupt controller data bus data bus port r usart0 twi spi tc0 usart0 spi tc0 usart0 twi port b aref aref sleep controller reset controller internal references ircom port f tc0 cpu xosc tosc crc watchdog oscillator bus matrix digital function analog function / oscillators programming, debug, test external clock / crystal pins general purpose i /o ground power
5 xmega d3 [datasheet] 8134m?avr?08/2013 3. overview the atmel avr xmega is a family of low power, high perfo rmance, and peripheral rich 8/16-bit microcontrollers based on the avr enhanced risc architecture. by executing instructions in a single clock cycle, the avr xmega devices achieve cpu throughput approaching one million instructions per second (mips) per megahertz, allowing the system designer to optimize power consumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumu lator or cisc based microcontrollers. the xmega d3 devices provide the following features: in- system programmable flash with read-while-write capabilities; internal eeprom and sram; four-channel event system and pr ogrammable multilevel interrupt controller, 50 general purpose i/o lines, 16-bit real-time counter (rtc); five, 16- bit timer/counters with compare and pwm channels; three usarts; two two-wire serial interfaces (twis); two seri al peripheral interfaces (spis); one sixteen-channel, 12-bit adc with programmable gain; two analog comparators (acs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with pll and prescaler; and programmable brown-out detection. the program and debug interface (pdi), a fast, two-pi n interface for programming and debugging, is available. the avr xmega devices have five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, event system, interrupt controller, and all peripherals to continue functioning. the power-down mode saves the sram and register contents, but stops the oscillato rs, disabling all other functions until the next twi, or pin- change interrupt, or reset. in power-save mode, the asynchr onous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. this allows very fast startup from the external crystal, combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce power consumption, the pe ripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. atmel offers a free qtouch library for embedding capacitive touch buttons, sliders and wheels functionality into avr microcontrollers. the devices are manufactured using atmel high-density, nonvol atile memory technology. the program flash memory can be reprogrammed in-system through the pdi. a boot loader runni ng in the device can use any interface to download the application program to the flash memory. the boot loader softwar e in the boot flash section will continue to run while the application flash section is updated, providing true read-while-w rite operation. by combining an 8/16-bit risc cpu with in-system, self-programmable flash, the avr xmega is a powerfu l microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. all avr xmega devices are supported with a full suite of program and system development tools, including: c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
6 xmega d3 [datasheet] 8134m?avr?08/2013 3.1 block diagram figure 3-1. xmega d3 block diagram. power supervision por/bod & reset port a (8) port b (8) sram adca aca ocd int. refs. pdi pa[0..7] pb[0..7] watchdog timer watchdog oscillator interrupt controller data bus prog/debug controller vcc gnd oscillator circuits/ clock generation oscillator control real time counter event system controller arefa arefb pdi_data reset/ pdi_clk sleep controller crc port c (8) pc[0..7] tcc0:1 usartc0 twic spic pd[0..7] pe[0..7] port d (8) tcd0 usartd0 spid tce0 usarte0 twie port e (8) tempref vcc/10 port r (2) xtal1 xtal2 pr[0..1] data bus nvm controller flash eeprom ircom bus matrix cpu tosc1 tosc2 tcf0 pf[0..7] port f (8) event routing network to clock generator digital function analog function / oscillators programming, debug, external cloc k / crystal pins general purpose i /o ground power
7 xmega d3 [datasheet] 8134m?avr?08/2013 4. resources a comprehensive set of development tools, application notes and datasheets are available for download on www.atmel.com/avr . 4.1 recommended reading ? atmel avr xmega d manual ? xmega application notes this device data sheet only contains part specific informati on with a short description of each peripheral and module. the xmega d manual describes the modules and peripherals in depth. the xmega application notes contain example code and show applied use of the modules and peripherals. all documentation are available from www.atmel.com/avr . 5. capacitive touch sensing the atmel qtouch library provides a simple to use soluti on to realize touch sensitive interfaces on most atmel avr microcontrollers. the patented charge-transfer signal acqui sition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the qtouch library includes support for the qtouch and atmel qmatrix acquisition methods. touch sensing can be added to any application by linki ng the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch channels and sensors, and then calling the touch sensing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: http://www.atmel.com/tools/qtouchlibrary.aspx . for implementation details and other information, refer to the qtouch library user guide - also available for download from the atmel website.
8 xmega d3 [datasheet] 8134m?avr?08/2013 6. avr cpu 6.1 features ? 8/16-bit, high-performance atmel avr risc cpu ? 137 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16mb of program memory and 16mb of data memory ? true 16/24-bit access to 16/24-bit i/o registers ? efficient support for 8-, 16- and 32-bit arithmetic ? configuration change protection of system-critical features 6.2 overview all atmel avr xmega devices use the 8/16-bit avr cpu. t he main function of the cpu is to execute the code and perform all calculations. the cpu is able to access memories , perform calculations, control peripherals, and execute the program in the flash memory. interrupt handling is described in a separate section, refer to ?interrupts and programmable multilevel interrupt controller? on page 27 . 6.3 architectural overview in order to maximize performance and parallelism, the avr cpu uses a harvard architecture with separate memories and buses for program and data. instructions in the program memo ry are executed with single-level pipelining. while one instruction is being executed, the next instruction is pre-fe tched from the program memory. this enables instructions to be executed on every clock cycle. for details of all avr instructions, refer to www.atmel.com/avr .
9 xmega d3 [datasheet] 8134m?avr?08/2013 figure 6-1. block diagram of the avr cpu architecture. the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed in t he alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. the alu is directly connected to the fast-access register f ile. the 32 * 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmet ic logic unit (alu) operation between registers or between a register and an immediate. six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. the memory spaces are linear. the data memory space and the program memory space are two different memory spaces. the data memory space is divided into i/o registers, sram, and external ram. in addition, the eeprom can be memory mapped in the data memory. all i/o status and control registers reside in the lowest 4kb addresses of the data memory. this is referred to as the i/o memory space. the lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3f. the rest is the extended i/o memory space, ranging from 0x0040 to 0x0fff. i/o registers here must be accessed as data space locations using load (ld/lds/ldd) and store (st/sts/std) instructions. the sram holds data. code execution from sram is not s upported. it can easily be accessed through the five different addressing modes supported in the avr architecture. the first sram address is 0x2000. data addresses 0x1000 to 0x1fff are reserved for memory mapping of eeprom. the program memory is divided in two sections, the applic ation program section and the boot program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that is used for self- programming of the application flash memory must reside in t he boot program section. the application section contains an application table section with separate lock bits for write and read/write protection. the application table section can be used for safe storing of nonvolatile data in the program memory.
10 xmega d3 [datasheet] 8134m?avr?08/2013 6.4 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed. the alu operates in direct connection with all 32 general purpose registers. in a single clock cycle, arithmetic oper ations between general purpose registers or between a register and an immediate are executed and the result is stored in the r egister file. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. alu operations are divided into three main categories ? ar ithmetic, logical, and bit functions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32- bit aritmetic. the hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 hardware multiplier the multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. the hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: ? multiplication of unsigned integers ? multiplication of signed integers ? multiplication of a signed integer with an unsigned integer ? multiplication of unsigned fractional numbers ? multiplication of signed fractional numbers ? multiplication of a signed fractional number with an unsigned one a multiplication takes two cpu clock cycles. 6.5 program flow after reset, the cpu starts to execute instructions from the lowest address in the flash programmemory ?0.? the program counter (pc) addresses the next instruction to be fetched. program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number use a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. after reset, the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu. 6.6 status register the status register (sreg) contains information about the result of the most recently executed arithmetic or logic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specif ied in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when ente ring an interrupt routine nor restored when returning from an interrupt. this must be handled by software. the status register is accessible in the i/o memory space. 6.7 stack and stack pointer the stack is used for storing return addresses after interrupts and subroutine calls. it can also be used for storing temporary data. the stack pointer (sp) register always points to the top of the stack. it is implemented as two 8-bit registers that are accessible in the i/o memory space. data are pushed and popped from the stack using the push and pop instructions. the stack grows from a higher memory locati on to a lower memory location. this implies that pushing data onto the stack decreases the sp, and popping data off the stack increases the sp. the sp is automatically loaded
11 xmega d3 [datasheet] 8134m?avr?08/2013 after reset, and the initial value is the highest address of the internal sram. if the sp is changed, it must be set to point above address 0x2000, and it must be defined before any subr outine calls are executed or before interrupts are enabled. during interrupts or subroutine calls, the return address is automatically pushed on the stack. the return address can be two or three bytes, depending on program memory size of the device. for devices with 128kb or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. for devices with more than 128kb of program memory, the return address is three bytes, and hence the sp is decremented/incremented by three. the return address is popped off the stack when returning from interrupts using the reti instruction, and from subroutine calls using the ret instruction. the sp is decremented by one when data are pushed on the stack with the push instruction, and incremented by one when data is popped off the stack using the pop instruction. to prevent corruption when updating the stack pointer from software, a write to spl will automatically disable interrupts for up to four instructions or until the next i/o memory write. after reset the stack pointer is initialized to the highest address of the sram. see figure 7-2 on page 15 . 6.8 register file the register file consists of 32 * 8-bit general purpose worki ng registers with single clock cycle access time. the register file supports the following input/output schemes: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input six of the 32 registers can be used as three 16-bit address r egister pointers for data space addressing, enabling efficient address calculations. one of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
12 xmega d3 [datasheet] 8134m?avr?08/2013 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and boot loader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or boot loader code ? separate read/write protection lock bits for all sections ? built in fast crc check of a select able flash program memory section ? data memory ? one linear address space ? single-cycle access from cpu ? sram ? eeprom ? byte and page accessible ? optional memory mapping for direct load and store ? i/o memory ? configuration and status registers for all peripherals and modules ? four bit-accessible general purpose registers for global variables or flags ? production signature row memory for factory programmed data ? id for each microcontroller device type ? serial number for each device ? calibration bytes for fact ory calibrated peripherals ? user signature row ? one flash page in size ? can be read and written from software ? content is kept after chip erase 7.2 overview the atmel avr architecture has two main memory spaces, the program memory and the data memory. executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. the data memory includes the internal sram, and eeprom for nonvol atile data storage. all memory spaces are linear and require no memory bank switching. nonvolatile memory (n vm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software. a separate memory section contains the fuse bytes. these are used for configuring important system functions, and can only be written by an external programmer. the available memory size configurations are shown in ?ordering information? on page 2 . in addition, each device has a flash memory signature row for calibration data, device identification, serial number etc. 7.3 flash program memory the atmel avr xmega devices contain on-chip, in-system reprogrammable flash memory for program storage. the flash memory can be accessed for read and write from an ex ternal programmer through the pdi or from application software running in the device. all avr cpu instructions are 16 or 32 bits wide, and each flas h location is 16 bits wide. the flash memory is organized in two main sections, the application section and the boot loader section. the sizes of the different sections are fixed, but
13 xmega d3 [datasheet] 8134m?avr?08/2013 device-dependent. these two sections have separate lock bits, and can have different levels of protection. the store program memory (spm) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. the application section contains an application table section with separate lock settings. this enables safe storage of nonvolatile data in the program memory. figure 7-1. flash program me mory (hexadecimal address). 7.3.1 application section the application section is the section of the flash that is used for storing the executable application code. the protection level for the application section can be selected by the boot lock bits for this section. the application section can not store any boot loader code since the spm instruction cannot be executed from the application section. 7.3.2 application table section the application table section is a part of the application sect ion of the flash memory that can be used for storing data. the size is identical to the boot loader section. the protection level for the application table section can be selected by the boot lock bits for this section. the possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. if this section is not used for data, application code can reside here. 7.3.3 boot loader section while the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the spm instruction can only initiate programming when executing fr om this section. the spm instruction can access the entire flash, including the boot lo ader section itself. the protection level for the boot loader section can be selected by the boot loader lock bits. if this section is not used for boot loader software, application code can be stored here. 7.3.4 production signature row the production signature row is a separate memory section for factory programmed data. it contains calibration data for functions such as oscillators and analog modules. some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. other va lues must be loaded from the signature row and written to the corresponding peripheral registers from software . for details on calibration conditions, refer to ?electrical characteristics? on page 63 . the production signature row also contains an id that identif ies each microcontroller device type and a serial number for each manufactured device. the serial number consists of the production lot number, wafer number, and wafer coordinates for the device. the device id for the available devices is shown in table 7-1 . word address atxmega 32d3 64d3 128d3 192d3 256d3 384d3 application section (32k/64k/128k/192k/256k/384k) 000000 ... 37ff 77ff efff 16fff 1efff 2efff application table section (4k/4k/8k/8k/8k/8k) 3800 7800 f000 17000 1f000 2f000 3fff 7fff ffff 17fff 1ffff 2ffff boot section (4k/4k/8k/8k/8k/8k) 4000 8000 10000 18000 20000 30000 47ff 87ff 10fff 18fff 20fff 30fff
14 xmega d3 [datasheet] 8134m?avr?08/2013 the production signature row cannot be written or erased, but it can be read from application software and external programmers. table 7-1. device id bytes. 7.3.5 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. it is one flash page in size, and is mean t for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 fuses and lock bits the fuses are used to configure important system functions , and can only be written from an external programmer. the application software can read the fuses. the fuses are used to configure reset sources such as brownout detector and watchdog, and startup configuration. the lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should b e blocked). lock bits can be written by external programmers and application software, but only to stricter protection levels. chip erase is the only way to erase the lock bits. to ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. an unprogrammed fuse or lock bit will have the value one, whil e a programmed fuse or lock bit will have the value zero. both fuses and lock bits are reprogrammable like the flash program memory. 7.5 data memory the data memory contains the i/o memory, internal sram , optionally memory mapped eeprom, and external memory if available. the data memory is organized as one continuous memory section, see figure 7-2 on page 15 . to simplify development, i/o memory, eeprom and sram will always hav e the same start addresses for all atmel avr xmega devices. device device id bytes byte 2 byte 1 byte 0 atxmega32d3 4a 95 1e atxmega64d3 4a 96 1e atxmega128d3 48 97 1e atxmega192d3 49 97 1e atxmega256d3 44 98 1e atxmega384d3 47 98 1e
15 xmega d3 [datasheet] 8134m?avr?08/2013 figure 7-2. data memory map (hexadecimal address). 7.6 eeprom all devices have eeprom for nonvolatile data storage. it is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. the eeprom supports both byte and page access. memory mapped eeprom allows highly efficient eeprom readi ng and eeprom buffer loading. when doing this, eeprom is accessible using load and store instructions. memory mapped eeprom will always start at hexadecimal address 0x1000. byte address atxmega32d3 byte address atxmega64d3 0 i/o registers (4k) 0 i/o registers (4k) fff fff 1000 eeprom (2k) 1000 eeprom (2k) 17ff 17ff reserved reserved 2000 internal sram (4k) 2000 internal sram (4k) 2fff 2fff byte address atxmega128d3 byte address atxmega192d3 0 i/o registers (4k) 0 i/o registers (4k) fff fff 1000 eeprom (2k) 1000 eeprom (2k) 17ff 17ff reserved reserved 2000 internal sram (8k) 2000 internal sram (16k) 3fff 5fff byte address atxmega256d3 byte address atxmega384d3 0 i/o registers (4k) 0 i/o registers (4k) fff fff 1000 eeprom (4k) 1000 eeprom (4k) 1fff 1fff 2000 internal sram (16k) 2000 internal sram (32k) 5fff 9fff
16 xmega d3 [datasheet] 8134m?avr?08/2013 7.7 i/o memory the status and configuration registers for peripherals and modules, including the cpu, are addressable through i/o memory locations. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, which are used to transfer data between the 32 registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range of 0x00 to 0x3f directly. in the address range 0x00 - 0x1f, single-cycle instructions for manipulation and c hecking of individual bits are available. the i/o memory address for all peripherals and modules is shown in the ?peripheral module address map? on page 54 . 7.7.1 general purpose i/o registers the lowest 16 i/o memory addresses are reserved as general purpose i/o registers. these registers can be used for storing global variables and flags, as they are directly bit- accessible using the sbi, cbi, sbis, and sbic instructions. 7.8 memory timing read and write access to the i/o memory takes one cpu clock cycle. a write to sram takes one cycle, and a read from sram takes two cycles. eeprom page load (write) takes one cycle, and three cycles are required for read. for burst read, new data are available every second cycle. refer to the instruction summary for more details on instructions and instruction timing. 7.9 device id and revision each device has a three-byte device id. this id identifies atmel as the manufacturer of the device and the device type. a separate register contains the revision number of the device. 7.10 i/o memory protection some features in the device are regarded as critical for safety in some applications. due to this, it is possible to lock the i/o register related to the clock system, the event system, and the advanced waveform extensions. as long as the lock is enabled, all related i/o registers are locked and they can not be written from the application software. the lock registers themselves are protected by the configuration change protection mechanism. 7.11 flash and eeprom page size the flash program memory and eeprom data memory are or ganized in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 7-2 on page 17 shows the flash program memory organization and program counter (pc) size. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the mo st significant bits in the address (fpage) give the page number and the least significant address bits (fword) give the word in the page.
17 xmega d3 [datasheet] 8134m?avr?08/2013 table 7-2. number of words and pages in the flash tbd. table 7-3 shows eeprom memory organization. eeeprom wr ite and erase operations can be performed one page or one byte at a time, while reading the eeprom is done one byte at a time. for eeprom access the nvm address register (addr[m:n]) is used for addressing. the most signi ficant bits in the address (e2page) give the page number and the least significant address bits (e2byte) give the byte in the page. table 7-3. number of byte s and pages in the eeprom. devices pc size flash size page size fword fpage application boot [bits] [bytes] [words] size no. of pages size no. of pages atxmega32d3 15 32k + 4k 128 z[7:1] z[15:7] 32k 128 4k 16 atxmega64d3 16 64k + 4k 128 z[7:1] z[16:9] 64k 256 4k 16 atxmega128d3 17 128k + 8k 256 z[8:1] z[17:9] 128k 256 8k 16 atxmega192d3 17 192k + 8k 256 z[8:1] z[17:9] 192k 384 8k 16 atxmega256d3 18 256k + 8k 256 z[8:1] z[18:9] 256k 512 8k 16 atxmega384d3 18 384k + 8k 256 z[8:1] z[19:9] 384k 768 8k 16 devices eeprom page size e2byte e2page no. of pages size [bytes] atxmega32d3 2k 32 addr[4:0] addr[10:5] 64 atxmega64d3 2k 32 addr[4:0] addr[10:5] 64 atxmega128d3 2k 32 addr[4:0] addr[10:5] 64 atxmega192d3 2k 32 addr[4:0] addr[10:5] 64 atxmega256d3 4k 32 addr[4:0] addr[11:5] 128 atxmega384d3 4k 32 addr[4:0] addr[11:5] 128
18 xmega d3 [datasheet] 8134m?avr?08/2013 8. event system 8.1 features ? system for direct peripheral-to- peripheral communication and signaling ? peripherals can directly send, receive, and react to peripheral events ? cpu independent operation ? 100% predictable signal timing ? short and guaranteed response time ? four event channels for up to four different and parallel signal routing configurations ? events can be sent and/or used by most peripherals, clock system, and software ? additional functions include ? quadrature decoders ? digital filtering of i/o pin state ? works in active mode and idle sleep mode 8.2 overview the event system enables direct peripheral-to-peripheral communication and signaling. it allows a change in one peripheral?s state to automatically trigger actions in other peripherals. it is designed to provide a predictable system for short and predictable response times between peripherals. it allows for autonomous peripheral control and interaction without the use of interrupts or cpu resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. it also allows for synch ronized timing of actions in several peripheral modules. a change in a peripheral?s state is referred to as an event, and usually corresponds to the peripheral?s interrupt conditions. events can be directly passed to other peripherals using a dedicated routing network called the event routing network. how events are routed and used by the peripherals is configured in software. figure 8-1 shows a basic diagram of all connected peripherals. the event system can directly connect together analog to digital converter, analog comparators, i/o port pins, the re al-time counter, timer/counters, and ir communication module (ircom). events can also be generated from software and the peripheral clock. figure 8-1. event system overvi ew and connected peripherals. the event routing network consists of four software-configurable multiplexers that control how events are routed and used. these are called event channels, and allow for up to four parallel event routing configurations. the maximum routing latency is two peripheral clock cycles. the event system works in both active mode and idle sleep mode. timer / counters adc real time counter port pins cpu / software ircom event routing network event system controller clk per prescaler ac
19 xmega d3 [datasheet] 8134m?avr?08/2013 9. system clock and clock options 9.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32mhz run-time calibrated and tuneable oscillator ? 2mhz run-time calibrated oscillator ? 32.768khz calibrated oscillator ? 32khz ultra low power (ulp) oscillator with 1khz output ? external clock options ? 0.4mhz - 16mhz crystal oscillator ? 32.768khz crystal oscillator ? external clock ? pll with 20mhz - 128mhz output frequency ? internal and external clock options and 1 to 31 multiplication ? lock detector ? clock prescalers with 1 to 2048 division ? fast peripheral clocks running at two and four times the cpu clock ? automatic run-time calibration of internal oscillators ? external oscillator and pll lock failure detection with optional non-maskable interrupt 9.2 overview atmel avr xmega d3 devices have a flexible clock system s upporting a large number of clock sources. it incorporates both accurate internal oscillators and external crysta l oscillator and resonator support. a high-frequency phase locked loop (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. an oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or pll fails. when a reset occurs, all clock sources except the 32khz ultra low power oscillator are disabled. after reset, the device will always start up running from the 2mhz internal oscill ator. during normal operation, the system clock source and prescalers can be changed from software at any time. figure 9-1 on page 20 presents the principal clock system. not all of the clocks need to be active at a given time. the clocks for the cpu and peripherals can be stopped using sleep modes and power reduction registers, as described in ?power management and sleep modes? on page 22 .
20 xmega d3 [datasheet] 8134m?avr?08/2013 figure 9-1. the clock system, clock sources and clock distribution. 9.3 clock sources the clock sources are divided in two main groups: internal oscillators and external clock sources. most of the clock sources can be directly enabled and disabled from softwa re, while others are automatically enabled or disabled, depending on peripheral settings. after reset, the device starts up running from the 2mhz internal oscillator. the other clock sources, dflls and pll, are turned off by default. the internal oscillators do not require any external component s to run. for details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. real time counter peripherals ram avr cpu non-volatile memory watchdog timer brown-out detector system clock prescalers system clock multiplexer (sclksel) pllsrc rtcsrc div32 32khz int. ulp 32.768khz int. osc 32.768khz tosc 2mhz int. osc 32mhz int. osc 0.4 ? 16mhz xtal div32 div32 div4 xoscsel pll tosc1 tosc2 xtal1 xtal2 clk sys clk rtc clk per2 clk per clk cpu clk per4
21 xmega d3 [datasheet] 8134m?avr?08/2013 9.3.1 32khz ultra low pow er internal oscillator this oscillator provides an approximate 32khz clock. the 32khz ultra low power (ulp) internal oscillator is a very low power clock source, and it is not designed for high accuracy. the oscillator employs a built-in prescaler that provides a 1khz output. the oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. this oscillator can be selected as the clock source for the rtc. 9.3.2 32.768khz calibrated internal oscillator this oscillator provides an approximate 32.768khz clock. it is calibrated during production to provide a default frequency close to its nominal frequency. the calibration register can also be written from software for run-time calibration of the oscillator frequency. the oscillator employs a built-in pre scaler, which provides both a 32.768khz output and a 1.024khz output. 9.3.3 32.768khz crystal oscillator a 32.768khz crystal oscillator can be connected between the tosc1 and tosc2 pins and enables a dedicated low frequency oscillator input circuit. a low power mode with reduc ed voltage swing on tosc2 is available. this oscillator can be used as a clock source for the system clock and rtc, and as the dfll reference clock. 9.3.4 0.4 - 16mhz crystal oscillator this oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16mhz. 9.3.5 2mhz run-time calibrated internal oscillator the 2mhz run-time calibrated internal oscillator is the default system clock source after reset. it is calibrated during production to provide a default frequency close to its nominal frequency. a dfll can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 9.3.6 32mhz run-time calib rated internal oscillator the 32mhz run-time calibrated internal oscillator is a high-frequency oscillator. it is calibrated during production to provide a default frequency close to its nominal frequency. a digital frequency looked loop (dfll) can be enabled for automatic run-time calibration of the oscillator to compens ate for temperature and voltage drift and optimize the oscillator accuracy. this oscillator can also be adjusted and calibrated to any frequency between 30mhz and 55mhz. 9.3.7 external clock sources the xtal1 and xtal2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. xtal1 can be used as input for an external clock signal . the tosc1 and tosc2 pins is dedicated to driving a 32.768khz crystal oscillator. 9.3.8 pll with 1x-31x multiplication factor the built-in phase locked loop (pll) can be used to generat e a high-frequency system clock. the pll has a user- selectable multiplication factor of from 1 to 31. in combin ation with the prescalers, this gives a wide range of output frequencies from all clock sources.
22 xmega d3 [datasheet] 8134m?avr?08/2013 10. power management and sleep modes 10.1 features ? power management for adjusting power consumption and functions ? five sleep modes ? idle ? power down ? power save ? standby ? extended standby ? power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 overview various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. this enables the atmel avr xmega microcontroller to stop unused modules to save power. all sleep modes are available and can be entered from active mode. in active mode, the cpu is executing application code. when the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. the application code decides which sleep m ode to enter and when. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. in addition, power reduction registers provide a method to st op the clock to individual peripherals from software. when this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 10.3 sleep modes sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. xmega microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. a dedicated sleep instruction (sleep) is avail able to enter sleep mode. interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. when an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the sleep instruction. if other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. after wake-up, the cpu is halted for four cycles before execution starts. the content of the register file, sram and registers are kept during sleep. if a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 10.3.1 idle mode in idle mode the cpu and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller and event system are kept running. any enabled interrupt will wake the device. 10.3.2 power-down mode in power-down mode, all clocks, including the real-time count er clock source, are stopped. this allows operation only of asynchronous modules that do not require a running clock. the only interrupts that can wake up the mcu are the two- wire interface address match interrupt and asynchronous port interrupts.
23 xmega d3 [datasheet] 8134m?avr?08/2013 10.3.3 power-save mode power-save mode is identical to power down, with one excepti on. if the real-time counter (rtc) is enabled, it will keep running during sleep, and the device can also wake up from either an rtc overflow or compare match interrupt. 10.3.4 standby mode standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the cpu, peripheral, and rtc clocks are stopped. this reduces the wake-up time. 10.3.5 extended standby mode extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the cpu and peripheral clocks are stopped. this reduces the wake-up time.
24 xmega d3 [datasheet] 8134m?avr?08/2013 11. system control and reset 11.1 features ? reset the microcontroller and set it to initial state when a reset source goes active ? multiple reset sources that cover different situations ? power-on reset ? external reset ? watchdog reset ? brownout reset ? pdi reset ? software reset ? asynchronous operation ? no running system clock in the device is required for reset ? reset status register for reading the reset source from the application code 11.2 overview the reset system issues a microcontroller reset and sets the device to its initial state. this is for situations where operation should not start or continue, such as when the micr ocontroller operates below its power supply rating. if a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. the i/o pins are immediately tri-stated. the program counter is set to the reset vector location, and all i/o registers are set to their initial values. the sram content is kept. however, if the device accesses the sram when a reset occurs, the content of the accessed location can not be guaranteed. after reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. by default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. the reset functionality is asynchronous, and so no running syst em clock is required to reset the device. the software reset feature makes it possible to issue a controlled system reset from the user software. the reset status register has individual status flags fo r each reset source. it is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 11.3 reset sequence a reset request from any reset source will immediately rese t the device and keep it in reset as long as the request is active. when all reset requests are released, the device will go through three stages before the device starts running again: ? reset counter delay ? oscillator startup ? oscillator calibration if another reset requests occurs during this process, the reset sequence will start over again.
25 xmega d3 [datasheet] 8134m?avr?08/2013 11.4 reset sources 11.4.1 power-on reset a power-on reset (por) is generated by an on-chip detection circuit. the por is activated when the v cc rises and reaches the por threshold voltage (v pot ), and this will start the reset sequence. the por is also activated to power down the device properly when the v cc falls and drops below the v pot level. the v pot level is higher for falling v cc than for rising v cc . consult the datasheet for por characteristics data. 11.4.2 brownout detection the on-chip brownout detection (bod) circuit monitors the v cc level during operation by comparing it to a fixed, programmable level that is selected by the bodlevel fuses. if disabled, bod is forced on at the lowest level during chip erase and when the pdi is enabled. 11.4.3 external reset the external reset circuit is connected to the external reset pin. the external reset will trigger when the reset pin is driven below the reset pin threshold voltage, v rst , for longer than the minimum pulse period, t ext . the reset will be held as long as the pin is kept low. the reset pin includes an internal pull-up resistor. 11.4.4 watchdog reset the watchdog timer (wdt) is a system function for monitoring correct program operation. if the wdt is not reset from the software within a programmable timeout period, a watchdog reset will be given. the watchdog reset is active for one to two clock cycles of the 2mhz internal oscillator. for more details see ?wdt ? watchdog timer? on page 26 . 11.4.5 software reset the software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.the reset will be issued within two cpu clock cycl es after writing the bit. it is not possible to execute any instruction from when a software reset is requested until it is issued. 11.4.6 program and debug interface reset the program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. this reset source is acce ssible only from external debuggers and programmers.
26 xmega d3 [datasheet] 8134m?avr?08/2013 12. wdt ? watchdog timer 12.1 features ? issues a device reset if the timer is not reset before its timeout period ? asynchronous operation from dedicated oscillator ? 1khz output of the 32khz ultra low power oscillator ? 11 selectable timeout periods, from 8ms to 8s ? two operation modes: ? normal mode ? window mode ? configuration lock to prevent unwanted changes 12.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situations such as runaway or deadlocked code. the wdt is a timer, configured to a predefined timeout period, and is constantly running when enabled. if the wdt is not reset within the timeout period, it will issue a microcontroller reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the window mode makes it possible to define a time slot or window inside the total timeout period during which wdt must be reset. if the wdt is reset outside this window, either too early or too late, a system reset will be issued. compared to the normal mode, this can also catch situat ions where a code error causes constant wdr execution. the wdt will run in active mode and all sleep modes, if e nabled. it is asynchronous, runs from a cpu-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. the configuration change protection mechanism ensures that the wdt settings cannot be changed by accident. for increased safety, a fuse for locking the wdt settings is also available.
27 xmega d3 [datasheet] 8134m?avr?08/2013 13. interrupts and programmable multilevel interrupt controller 13.1 features ? short and predictable interrupt response time ? separate interrupt configuration and vector address for each interrupt ? programmable multilevel interrupt controller ? interrupt prioritizing according to level and vector address ? three selectable interrupt levels for all interrupts: low, medium, and high ? selectable, round-robin priority scheme within low-level interrupts ? non-maskable interrupts for critical functions ? interrupt vectors optionally placed in the application section or the boot loader section 13.2 overview interrupts signal a change of state in peripherals, and this c an be used to alter program execution. peripherals can have one or more interrupts, and all are individually enabled and configured. when an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. the programmable multilevel interrupt controller (pmic) controls the handling and prioritizing of interrupt requests. when an interrupt request is acknowledged by the pmic, the program counter is set to point to t he interrupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority leve ls for their interrupts: low, medium, and high. interrupts are prioritized according to their level and their interrupt vect or address. medium-level interrupts will interrupt low-level interrupt handlers. high-level interrupts wil l interrupt both medium- and low-level interrupt handlers. within each level, the interrupt priority is decided from the interrupt vector addres s, where the lowest interrupt vector address has the highest interrupt priority. low-level interrupts have an optional r ound-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) are also supported, and can be used for system critical functions. 13.3 interrupt vectors the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the atmel avr xmega d3 devices are shown in table 13-1 on page 28 . offset addresses for each interrupt available in the peripheral ar e described for each peripheral in the xmega d manual. for peripherals or modules that have only one inte rrupt, the interrupt vector is shown in table 13-1 on page 28 . the program address is the word address.
28 xmega d3 [datasheet] 8134m?avr?08/2013 table 13-1. reset and interrupt vectors. program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillator failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base 0x008 portr_int_base port r interrupt base 0x014 rtc_int_base real time counter interrupt base 0x018 twic_int_base two-wire interface on port c interrupt base 0x01c tcc0_int_base timer/counter 0 on port c interrupt base 0x028 tcc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x040 nvm_int_base non-volatile memory interrupt base 0x044 portb_int_base port b interrupt base 0x056 porte_int_base port e int base 0x05a twie_int_base two-wire interface on port e interrupt base 0x05e tce0_int_base timer/counter 0 on port e interrupt base 0x074 usarte0_int_base usart 0 on port e interrupt base 0x080 portd_int_base port d interrupt base 0x084 porta_int_base port a interrupt base 0x088 aca_int_base analog comparator on port a interrupt base 0x08e adca_int_base analog to digital converter on port a interrupt base 0x09a tcd0_int_base timer/counter 0 on port d interrupt base 0x0ae spid_int_vector spi d interrupt vector 0x0b0 usartd0_int_base usart 0 on port d interrupt base 0x0b6 usartd1_int_base usart 1 on port d interrupt base 0x0d0 portf_int_base port f interrupt base 0x0d8 tcf0_int_base timer/counter 0 on po rt f interrupt base
29 xmega d3 [datasheet] 8134m?avr?08/2013 14. i/o ports 14.1 features ? 50 general purpose input and output pins with individual configuration ? output driver with configurable driver and pull settings: ? totem-pole ? wired-and ? wired-or ? bus-keeper ? inverted i/o ? input with synchronous and/or asynchronous sensing with interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? optional pull-up and pull-down resistor on input and wired-or/and configuration ? asynchronous pin change sensing that can wake the device from all sleep modes ? two port interrupts with pin masking per i/o port ? efficient and safe access to port pins ? hardware read-modify-write through de dicated toggle/clear/set registers ? configuration of multiple pins in a single operation ? mapping of port registers into bit-accessible i/o memory space ? peripheral clocks output on port pin ? real-time counter clock output to port pin ? event channels can be output on port pin ? remapping of digital peripheral pin functions ? selectable usart, spi, and timer/counter input/output pin locations 14.2 overview one port consists of up to eight port pins: pin 0 to 7. each port pin can be configured as input or output with configurable driver and pull settings. they also implement synchronous an d asynchronous input sensing with interrupts and events for selectable pin change conditions. asynchronous pin-change sensin g means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. all functions are individual and configurable per pin, but se veral pins can be configured in a single operation. the pins have hardware read-modify-write (rmw) functionality for safe and correct change of drive value and/or pull resistor configuration. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the port pin configuration also controls input and output selection of other device functions. it is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. the same applies to events from the event system that can be used to synchronize and cont rol external functions. other digital peripherals, such as usart, spi, and timer/counters, can be remapped to selectabl e pin locations in order to optimize pin-out versus application needs. the notation of the ports are porta, portb, portc, portd, porte, portf and portr.
30 xmega d3 [datasheet] 8134m?avr?08/2013 14.3 output driver all port pins (pn) have programmable output configuration. 14.3.1 push-pull figure 14-1. i/o configuration - totem-pole. 14.3.2 pull-down figure 14-2. i/o configuration - totem-pole with pull-down (on input). 14.3.3 pull-up figure 14-3. i/o configuration - totem-pole with pull-up (on input). inn outn dirn pn inn outn dirn pn inn outn dirn pn
31 xmega d3 [datasheet] 8134m?avr?08/2013 14.3.4 bus-keeper the bus-keeper?s weak output produces the same logical level as the last output level. it acts as a pull-up if the last level was ?1?, and pull-down if the last level was ?0?. figure 14-4. i/o configuration - totem-pole with bus-keeper. 14.3.5 others figure 14-5. output configuration - wired-or with optional pull-down. figure 14-6. i/o conf iguration - wired-and wi th optional pull-up. inn outn dirn pn inn outn pn inn outn pn
32 xmega d3 [datasheet] 8134m?avr?08/2013 14.4 input sensing input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 14-7 . figure 14-7. input sensing system overview. when a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 14.5 alternate port functions most port pins have alternate pin functions in addition to being a general purpose i/o pin. when an alternate function is enabled, it might override the normal port pin function or pin va lue. this happens when other per ipherals that require pins are enabled or configured to use pins. if and how a peripheral will override and use pins is described in the section for that peripheral. ?pinout and pin functions? on page 49 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. d q r inverted i/o interrupt control d q r pxn synchronizer inn edge detect synchronous sensing edge detect asynchronous sensing irq synchronous events asynchronous events
33 xmega d3 [datasheet] 8134m?avr?08/2013 15. tc0/1 ? 16-bit timer/ counter type 0 and 1 15.1 features ? five 16-bit timer/counters ? four timer/counters of type 0 ? one timer/counter of type 1 ? split-mode enabling two 8-bit timer/count er from each timer/counter type 0 ? 32-bit timer/counter support by cascading two timer/counters ? up to four compare or capture (cc) channels ? four cc channels for ti mer/counters of type 0 ? two cc channels for timer/counters of type 1 ? double buffered timer period setting ? double buffered capture or compare channels ? waveform generation: ? frequency generation ? single-slope pulse width modulation ? dual-slope pulse width modulation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? timer overflow and error interrupts/events ? one compare match or input capture interrupt/event per cc channel ? can be used with event system for: ? quadrature decoding ? count and direction control ? capture ? high-resolution extension ? increases frequency and waveform resolu tion by 4 (2-bit) or 8 (3-bit) ? advanced waveform extension: ? low- and high-side output with pr ogrammable dead-time insertion (dti) ? event controlled fault protection for safe disabling of drivers 15.2 overview atmel avr xmega d3 devices have a set of five flexible 16- bit timer/counters (tc). their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. a timer/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period setting that can be used for timing. the cc channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. a timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. a timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. the event system can also be used for direction cont rol and capture trigger or to synchronize operations.
34 xmega d3 [datasheet] 8134m?avr?08/2013 there are two differences between timer/counter type 0 and type 1. timer/counter 0 has four cc channels, and timer/counter 1 has two cc channels. all information related to cc channels 3 and 4 is valid only for timer/counter 0. only timer/counter 0 has the split mode feature that split it into two 8-bit timer/counters with four compare channels each. some timer/counters have extensions to enable more specialized waveform and frequency generation. the advanced waveform extension (awex) is intended for motor control and other power control applications. it enables low- and high- side output with dead-time insertion, as well as fault protecti on for disabling and shutting down external drivers. it can also generate a synchronized bit pattern across the port pins. the advanced waveform extension can be enabled to provide extra and more advanced features for the timer/counter. this are only available for timer/counter 0. see ?awex ? advanced waveform extension? on page 36 for more details. the high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. see ?hi-res ? high resolution extension? on page 37 for more details. figure 15-1. overview of a timer/coun ter and closely related peripherals. portc has one timer/counter 0 and one timer/counter1. portd, porte and portf each has one timer/counter 0. notation of these are tcc0 (time/counter c0), tcc1, tcd0, tce0, and tcf0, respectively. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dead-time insertion pattern generation clk per4 port event system clk per timer/counter
35 xmega d3 [datasheet] 8134m?avr?08/2013 16. tc2 ? timer/counter type 2 16.1 features ? eight 8-bit timer/counters ? four low-byte timer/counter ? four high-byte timer/counter ? up to eight compare channels in each timer/counter 2 ? four compare channels for the low-byte timer/counter ? four compare channels for the high-byte timer/counter ? waveform generation ? single slope pulse width modulation ? timer underflow interrupts/events ? one compare match interrupt/event per compare channel for the low-byte timer/counter ? can be used with the event system for count control 16.2 overview there are four timer/counter 2. these are realized when a timer/counter 0 is set in split mode. it is then a system of two eight-bit timer/counters, each with four compare channels. this results in eight configurable pulse width modulation (pwm) channels with individually controlled duty cycles, and is intended for applications that require a high number of pwm channels. the two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. the difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts and events. the two eight-bit timer/counters have a shared clock source and separate period and compare settings. they can be clocked and timed from the periphe ral clock, with optional prescaling, or from the event system. the counters are always counting down. portc, portd, porte and portf each has one timer/counter 2. notation of these are tcc2 (timer/counter c2), tcd2, tce2 and tcf2, respectively.
36 xmega d3 [datasheet] 8134m?avr?08/2013 17. awex ? advanced waveform extension 17.1 features ? waveform output with complementary output from each compare channel ? four dead-time insertion (dti) units ? 8-bit resolution ? separate high and low side dead-time setting ? double buffered dead time ? optionally halts timer during dead-time insertion ? pattern generation unit creating synchronised bit pattern across the port pins ? double buffered pattern generation ? optional distribution of one compar e channel output across the port pins ? event controlled fault protection for instant and predictable fault triggering 17.2 overview the advanced waveform extension (awex) provides extra func tions to the timer/counter in waveform generation (wg) modes. it is primarily intended for use with different types of motor control and other power control applications. it enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. it can also generate a synchronized bit pattern across the port pins. each of the waveform generator outputs from the timer/count er 0 are split into a complimentary pair of outputs when any awex features are enabled. these output pairs go through a dead-time insertion (dti) unit that generates the non- inverted low side (ls) and inverted high side (hs) of the wg output with dead-time insertion between ls and hs switching. the dti output will override the normal port value according to the port override setting. the pattern generation unit can be used to generate a synchroniz ed bit pattern on the port it is connected to. in addition, the wg output from compare channel a can be distributed to and override all the port pins. when the pattern generator unit is enabled, the dti unit is bypassed. the fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the awex output. the event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. the awex is available for tcc0. the notation of this is awexc.
37 xmega d3 [datasheet] 8134m?avr?08/2013 18. hi-res ? high r esolution extension 18.1 features ? increases waveform generator resolution up to 8 (three bits) ? supports frequency, single-slope pwm, and dual-slope pwm generation ? supports the awex when this is used for the same timer/counter 18.2 overview the high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. it can be used for a time r/counter doing frequency, single-slope pwm, or dual-slope pwm generation. it can also be used with the awex if this is used for the same timer/counter. the hi-res extension uses the peripheral 4 clock (clk per4 ). the system clock prescalers must be configured so the peripheral 4 clock frequency is four times higher t han the peripheral and cpu clock frequency when the hi-res extension is enabled. there is one hi-res extensions that can be enabled for timer/counters pair on portc. the notation of this is hiresc.
38 xmega d3 [datasheet] 8134m?avr?08/2013 19. rtc ? 16-bit real-time counter 19.1 features ? 16-bit resolution ? selectable clock source ? 32.768khz external crystal ? external clock ? 32.768khz internal oscillator ? 32khz internal ulp oscillator ? programmable 10-bit clock prescaling ? one compare register ? one period register ? clear counter on period overflow ? optional interrupt/event on overflow and compare match 19.2 overview the 16-bit real-time counter (rtc) is a counter that typica lly runs continuously, including in low-power sleep modes, to keep track of time. it can wake up the device from sleep modes and/or interrupt the device at regular intervals. the reference clock is typically the 1.024khz output from a high-accuracy crystal of 32.768khz, and this is the configuration most optimized for low power consumption. the faster 32.768khz output can be selected if the rtc needs a resolution higher than 1ms. the rtc can also be clock ed from an external clock signal, the 32.768khz internal oscillator or the 32khz internal ulp oscillator. the rtc includes a 10-bit programmable prescaler that c an scale down the reference clock before it reaches the counter. a wide range of resolutions and time-out periods can be configured. with a 32.768khz clock source, the maximum resolution is 30.5s, and time-out periods can range up to 2000 seconds. with a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). the rtc can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. figure 19-1. real-time counter overview. 32.768khz crystal osc 32.768khz int. osc tosc1 tosc2 external clock div32 div32 32khz int ulp (div32) rtcsrc 10-bit prescaler clk rtc cnt per comp = = ?match?/ compare top/ overflow
39 xmega d3 [datasheet] 8134m?avr?08/2013 20. twi ? two-wire interface 20.1 features ? two identical two-wire interface peripherals ? bidirectional, two-wire communication interface ? phillips i 2 c compatible ? system management bus (smbus) compatible ? bus master and slave operation supported ? slave operation ? single bus master operation ? bus master in multi-master bus environment ? multi-master arbitration ? flexible slave address match functions ? 7-bit and general call address recognition in hardware ? 10-bit addressing supported ? address mask register for dual address match or address range masking ? optional software address recognition for unlimited number of addresses ? slave can operate in all sleep modes, including power-down ? slave address match can wake device from all sleep modes ? 100khz and 400khz bus frequency support ? slew-rate limited output drivers ? input filter for bus noise and spike suppression ? support arbitration between start/r epeated start and data bit (smbus) ? slave arbitration allows support for addr ess resolve protocol (arp) (smbus) 20.2 overview the two-wire interface (twi) is a bidirectional, two-wire communication interface. it is i 2 c and system management bus (smbus) compatible. the only external hardware needed to im plement the bus is one pull-up resistor on each bus line. a device connected to the bus must act as a master or a slave. the master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. one bus can have many slaves and one or several masters that can take control of the bus. an arbitration process handles priority if more than one master tries to transmit data at the same time. mechanisms for resolving bus contention are inherent in the protocol. the twi module supports master and slave functionality. t he master and slave functionality are separated from each other, and can be enabled and configured separately. the ma ster module supports multi-master bus operation and arbitration. it contains the baud rate generator. both 100khz and 400khz bus frequency is supported. quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. the slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a register for address range masking. the slave continues to operate in all sleep modes, including power-down mode. this enables the slave to wake up the device from all sleep modes on twi address match. it is possible to disable the address matching to let this be handled in software instead. the twi module will detect start and stop conditions, bus collisions, and bus errors. arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. it is possible to disable the twi drivers in the device, and enable a four-wire digital interface for connecting to an external twi bus driver. this can be used for applications where the device operates from a different v cc voltage than used by the twi bus. portc and porte each has one twi. notation of these peripherals are twic and twie.
40 xmega d3 [datasheet] 8134m?avr?08/2013 21. spi ? serial pe ripheral interface 21.1 features ? two identical spi peripherals ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? eight programmable bit rates ? interrupt flag at the end of transmission ? write collision flag to indicate data collision ? wake up from idle sleep mode ? double speed master mode 21.2 overview the serial peripheral interface (spi) is a high-speed synchr onous data transfer interface using three or four pins. it allows fast communication between an atmel avr xmega device and peripheral devices or between several microcontrollers. the spi supports full-duplex communication. a device connected to the bus must act as a master or slave. the master initiates and controls all data transactions. portc and portd each has one spi. notation of thes e peripherals are spic and spid, respectively.
41 xmega d3 [datasheet] 8134m?avr?08/2013 22. usart 22.1 features ? three identical usart peripherals ? full-duplex operation ? asynchronous or synchronous operation ? synchronous clock rates up to 1/2 of the device clock frequency ? asynchronous clock rates up to 1/8 of the device clock frequency ? supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits ? fractional baud rate generator ? can generate desired baud rate from any system clock frequency ? no need for external oscillator with certain frequencies ? built-in error detection and correction schemes ? odd or even parity generation and parity check ? data overrun and framing error detection ? noise filtering includes false start bit detection and digital low-pass filter ? separate interrupts for ? transmit complete ? transmit data register empty ? receive complete ? multiprocessor communication mode ? addressing scheme to address a specif ic devices on a multidevice bus ? enable unaddressed devices to automatically ignore all frames ? master spi mode ? double buffered operation ? operation up to 1/2 of the peripheral clock frequency ? ircom module for irda compliant pulse modulation/demodulation 22.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a fast and flexible serial communication module. the usart supports full-duplex communication and asynchronous and synchronous operation. the usart can be configured to operate in spi master mode and used for spi communication. communication is frame based, and the frame format c an be customized to support a wide range of standards. the usart is buffered in both directions, enabling continued dat a transmission without any delay between frames. separate interrupts for receive and transmit complete enable fully interrupt driven communication. frame error and buffer overflow are detected in hardware and indicated with separate st atus flags. even or odd parity generation and parity check can also be enabled. the clock generator includes a fractional baud rate generator that is able to generate a wide range of usart baud rates from any system clock frequencies. this removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. it also supports ex ternal clock input in synchronous slave operation. when the usart is set in master spi mode, all usart-spec ific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. pin control and interrupt generation are identical in both modes. the registers are used in both modes, but their functionality differs for some control settings. an ircom module can be enabled for one usart to suppor t irda 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. portc, portd, and porte each has one usart. notati on of these peripherals are usartc0, usartd0 and usarte0, respectively.
42 xmega d3 [datasheet] 8134m?avr?08/2013 23. ircom ? ir communication module 23.1 features ? pulse modulation/demodulation for infrared communication ? irda compatible for baud rates up to 115.2kbps ? selectable pulse modulation scheme ? 3/16 of the baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built-in filtering ? can be connected to and used by any usart 23.2 overview atmel avr xmega devices contain an infrared communication mo dule (ircom) that is irda compatible for baud rates up to 115.2kbps. it can be connected to any usart to enable infrared pulse encoding/decoding for that usart.
43 xmega d3 [datasheet] 8134m?avr?08/2013 24. crc ? cyclic redu ndancy check generator 24.1 features ? cyclic redundancy check (crc) generation and checking for ? communication data ? program or data in flash memory ? data in sram and i/o memory space ? integrated with flash memory and cpu ? automatic crc of the complete or a selectable range of the flash memory ? cpu can load data to the crc generator through the i/o interface ? crc polynomial software selectable to ? crc-16 (crc-ccitt) ? crc-32 (ieee 802.3) ? zero remainder detection 24.2 overview a cyclic redundancy check (crc) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a dat a transmission, and data present in the data and program memories. a crc takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. when the same data are later received or read, the device or application repeats the calculation. if the new crc result does not match the one calculated earlier, the block contains a data error. the application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. typically, an n-bit crc applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 -n of all longer error bursts. the crc module in atmel avr xmega devices s upports two commonly used crc polynomials; crc-16 (crc- ccitt) and crc-32 (ieee 802.3). crc-16: polynominal: x 16 +x 12 +x 5 +1 hex value: 0x1021 crc-32: polynominal: x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 hex value: 0x04c11db7
44 xmega d3 [datasheet] 8134m?avr?08/2013 25. adc ? 12-bit analog to digital converter 25.1 features ? one analog to digital converter (adc) ? 12-bit resolution ? up to 300 thousand samples per second ? down to 2.3s conversion time with 8-bit resolution ? down to 3.35s conversion time with 12-bit resolution ? differential and single-ended input ? 16 single-ended inputs ? 16 * 4 differential inputs without gain ? 8 * 4 differential input with gain ? built-in differential gain stage ? 1/2, 1, 2, 4, 8, 16, 32 and 64 gain options ? single, continuous and scan conversion options ? three internal inputs ? internal temperature sensor ? v cc voltage divided by 10 ? 1.1v bandgap voltage ? internal and external reference options ? compare function for accurate monitoring of user defined thresholds ? optional event triggered conversion for accurate timing ? optional interrupt/event on compare result 25.2 overview the adc converts analog signals to digital values. the adc has 12-bit resolution and is capable of converting up to 300 thousand samples per second (ksps). the input select ion is flexible, and both single-ended and differential measurements can be done. for differential measurements, an op tional gain stage is available to increase the dynamic range. in addition, several internal signal inputs are available. the adc can provide both signed and unsigned results. the adc measurements can either be started by applicati on software or an incoming event from another peripheral in the device. the adc measurements can be started with predictable timing, and without software intervention. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the v cc /10 and the bandgap voltage can also be measured by the adc. the adc has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required.
45 xmega d3 [datasheet] 8134m?avr?08/2013 figure 25-1. adc overview. the adc may be configured for 8- or 12-bit result, reducin g the minimum conversion time (propagation delay) from 3.35s for 12-bit to 2.3s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). porta has one adc. notation of this peripheral is adca. ch0 result compare register < > threshold (int req) internal 1.00v internal vcc/1.6v arefa arefb v inp v inn internal signals internal vcc/2 adc0 adc15 ? ? ? adc0 adc7 ? ? ? reference voltage adc
46 xmega d3 [datasheet] 8134m?avr?08/2013 26. ac ? analog comparator 26.1 features ? two analog comparators (ac) ? selectable hysteresis ? no ? small ? large ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? bandgap reference voltage ? a 64-level programmable voltage scaler of the internal v cc voltage ? interrupt and event generation on: ? rising edge ? falling edge ? toggle ? window function interrupt and event generation on: ? signal above window ? signal inside window ? signal below window ? constant current source with configurable output pin selection 26.2 overview the analog comparator (ac) compares the voltage levels on two inputs and gives a digital output based on this comparison. the analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. the analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application. the input selection includes analog port pins, several inter nal signals, and a 64-level programmable voltage scaler. the analog comparator output state can also be output on a pin for use by external devices. a constant current source can be enabled and output on a selectable pin. this can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. the analog comparators are always grouped in pairs on eac h port. these are called analog comparator 0 (ac0) and analog comparator 1 (ac1). they have identical behavior, but separate control registers. used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. porta has one ac pair. notation is aca.
47 xmega d3 [datasheet] 8134m?avr?08/2013 figure 26-1. analog comparator overview. the window function is realized by connecting the external i nputs of the two analog comparators in a pair as shown in figure 26-2 . figure 26-2. analog comparator window function. acnmuxctrl acnctrl interrupt mode enable enable hysteresis hysteresis ac1out winctrl interrupt sensititivity control & window function events interrupts ac0out pin input pin input pin input pin input voltage scaler bandgap + - + - ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
48 xmega d3 [datasheet] 8134m?avr?08/2013 27. programming and debugging 27.1 features ? programming ? external programming through pdi interface ? minimal protocol overhead for fast operation ? built-in error detection and handling for reliable operation ? boot loader support for programming through any communication interface ? debugging ? nonintrusive, real-time, on-chip debug system ? no software or hardware resources required from device except pin connection ? program flow control ? go, stop, reset, step into, step over, step out, run-to-cursor ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, break on: ? data location read, write, or both read and write ? data location content equal or not equal to a value ? data location content is great er or smaller than a value ? data location content is within or outside a range ? no limitation on device clock frequency ? program and debug interface (pdi) ? two-pin interface for external programming and debugging ? uses the reset pin and a dedicated pin ? no i/o pins required during programming or debugging 27.2 overview the program and debug interface (pdi) is an atmel proprie tary interface for external programming and on-chip debugging of a device. the pdi supports fast programming of nonvolatile memory (n vm) spaces; flash, eepom, fuses, lock bits, and the user signature row. debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. it does not require any software or hardware resources except for the device pin connection. using the atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. application debug can be done from a c or other high-level language source code level, as well as from an assembler and disassembler level. programming and debugging can be done through the pdi physical layer. this is a two-pin interface that uses the reset pin for the clock input (pdi_clk) and one other dedicated pi n for data input and output (pdi_data). any external programmer or on-chip debugger/emulator can be directly connected to this interface.
49 xmega d3 [datasheet] 8134m?avr?08/2013 28. pinout and pin functions the device pinout is shown in ?pinout/block diagram? on page 4 . in addition to general purpose i/o functionality, each pin can have several alternate functions. this will depend on which peripheral is enabled and connected to the actual pin. only one of the pin functions can be used at time. 28.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 28.1.1 operation/power supply 28.1.2 port interrupt functions 28.1.3 analog functions 28.1.4 timer/counter and awex functions v cc digital supply voltage av cc analog supply voltage gnd ground sync port pin with full synchronous and limi ted asynchronous interrupt function async port pin with full synchronous and full asynchronous interrupt function acn analog comparator input pin n acnout analog comparator n output adcn analog to digital converter input pin n a ref analog reference input pin ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n
50 xmega d3 [datasheet] 8134m?avr?08/2013 28.1.5 communication functions 28.1.6 oscillators, clock and event 28.1.7 debug/system functions 28.2 alternate pin functions the tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. the head row shows what peripheral that enable and use the alternate pin functions. for better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under th e first table where this apply. scl serial clock for twi sda serial data for twi sclin serial clock in for twi when external driver interface is enabled sclout serial clock out for twi when external driver interface is enabled sdain serial data in for twi when external driver interface is enabled sdaout serial data out for twi when external driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi toscn timer oscillator pin n xtaln input/output for oscillator pin n clkout peripheral clock output evout event channel output rtcout rtc clock source output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin
51 xmega d3 [datasheet] 8134m?avr?08/2013 table 28-1. port a - alternate functions. table 28-2. port b - alternate functions. table 28-3. port c - alternate functions. port a pin # interrupt adca pos/ gainpos adca neg adca gainneg aca pos aca neg aca out refa gnd 60 avcc 61 pa0 62 sync adc0 adc0 ac0 ac0 arefa pa1 63 sync adc1 adc1 ac1 ac1 pa2 64 sync/async adc2 adc2 ac2 pa3 1 sync adc3 adc3 ac3 ac3 pa4 2 sync adc4 adc4 ac4 pa5 3 sync adc5 adc5 ac5 ac5 pa6 4 sync adc6 adc6 ac6 ac1out pa7 5 sync adc7 adc7 ac7 ac0out port b pin # interrupt adca pos refb pb0 6 sync adc8 arefb pb1 6 sync adc9 pb2 8 sync/async adc10 pb3 9 sync adc11 pb4 10 sync adc12 pb5 11 sync adc13 pb6 12 sync adc14 pb7 13 sync adc15 gnd 14 vcc 15 port c pin # interrupt tcc0 (1)(2) awexc tcc1 usartc0 (3) spic (4) twic clockout (5) eventout (6) pc0 16 sync oc0a oc0als sda pc1 17 sync oc0b oc0ahs xck0 scl pc2 18 sync/async oc0c oc0bls rxd0 pc3 19 sync oc0d oc0bhs txd0 pc4 20 sync oc0cls oc1a ss pc5 21 sync oc0chs oc1b mosi
52 xmega d3 [datasheet] 8134m?avr?08/2013 notes: 1. pin mapping of all tc0 can optionally be moved to high nibble of port. 2. if tc0 is configured as tc2 all eight pins can be used for pwm output. 3. pin mapping of all usart0 can optionally be moved to high nibble of port. 4. pins mosi and sck for all spi can optionally be swapped. 5. clkout can optionally be moved between port c, d, and e and between pin 4 and 7. 6. evout can optionally be moved between port c, d, and e and between pin 4 and 7. table 28-4. port d - alternate functions. table 28-5. port e - alternate functions. pc6 22 sync oc0dls miso rtcout pc7 23 sync oc0dhs sck clk per evout gnd 24 vcc 25 port c pin # interrupt tcc0 (1)(2) awexc tcc1 usartc0 (3) spic (4) twic clockout (5) eventout (6) port d pin # interrupt tcd0 usartd0 spid clockout eventout pd0 26 sync oc0a pd1 27 sync oc0b xck0 pd2 28 sync/async oc0c rxd0 pd3 29 sync oc0d txd0 pd4 30 sync ss pd5 31 sync mosi pd6 32 sync miso pd7 33 sync sck clk per evout gnd 34 vcc 35 port e pin # interrupt tce0 usarte0 tosc twie clockout eventout pe0 36 sync oc0a sda pe1 37 sync oc0b xck0 scl pe2 38 sync/async oc0c rxd0 pe3 39 sync oc0d txd0 pe4 40 sync pe5 41 sync pe6 42 sync tosc2 pe7 43 sync tosc1 clk per evout gnd 44 vcc 45
53 xmega d3 [datasheet] 8134m?avr?08/2013 table 28-6. port f - alternate functions. table 28-7. port r - alternate functions. port f pin # interrupt tcf0 pf0 46 sync oc0a pf1 47 sync oc0b pf2 48 sync/async oc0c pf3 49 sync oc0d pf4 50 sync pf5 51 sync pf6 54 sync pf7 55 sync gnd 52 vcc 53 port r pin # interrupt pdi xtal pdi 56 pdi_data reset 57 pdi_clock pro 58 sync xtal2 pr1 59 sync xtal1
54 xmega d3 [datasheet] 8134m?avr?08/2013 29. peripheral module address map the address maps show the base address for each peripher al and module in atmel avr xmega d3. for complete register description and summary for each peripheral module, refer to the xmega d manual . table 29-1. peripheral module address map. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 2 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32mhz internal oscillator 0x0068 dfllrc2m dfll for the 2mhz internal oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 wdt watchdog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x0180 evsys event system 0x00d0 crc crc module 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0380 aca analog comparator pair on port a 0x0400 rtc real-time counter 0x0480 twic two-wire interface on port c 0x04a0 twie two-wire interface on port e 0x0600 porta port a 0x0620 portb port b 0x0640 portc port c
55 xmega d3 [datasheet] 8134m?avr?08/2013 0x0660 portd port d 0x0680 porte port e 0x06a0 portf port f 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 awexc advanced waveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0900 tcd0 timer/counter 0 on port d 0x09a0 usartd0 usart 0 on port d 0x09c0 spid serial peripheral interface on port d 0x0a00 tce0 timer/counter 0 on port e 0x0a80 awexe advanced waveform extension on port e 0x0aa0 usarte0 usart 0 on port e 0x0ac0 spie serial peripheral interface on port e 0x0b00 tcf0 timer/counter 0 on port f base address name description
56 xmega d3 [datasheet] 8134m?avr?08/2013 30. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd ? rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd ? rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd ? rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd ? rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd ? rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd ? rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd ? rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd ? rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd ? rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd ? rd ? k z,n,v,s 1 or rd, rr logical or rd ? rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd ? rd v k z,n,v,s 1 eor rd, rr exclusive or rd ? rd ? rr z,n,v,s 1 com rd one?s complement rd ? $ff - rd z,c,n,v,s 1 neg rd two?s complement rd ? $00 - rd z,c,n,v,s,h 1 sbr rd, k set bit(s) in register rd ? rd v k z,n,v,s 1 cbr rd, k clear bit(s) in register rd ? rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd ? rd + 1 z,n,v,s 1 dec rd decrement rd ? rd - 1 z,n,v,s 1 tst rd test for zero or minus rd ? rd ? rd z,n,v,s 1 clr rd clear register rd ? rd ? rd z,n,v,s 1 ser rd set register rd ? $ff none 1 mul rd, rr multiply unsigned r1:r0 ? rd x rr (uu) z,c 2 muls rd, rr multiply signed r1:r0 ? rd x rr (ss) z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 ? rd x rr (su) z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 ? rd x rr<<1 (uu) z,c 2 fmuls rd, rr fractional multiply signed r1:r0 ? rd x rr<<1 (ss) z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? rd x rr<<1 (su) z,c 2 branch instructions rjmp k relative jump pc ? pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) ? ? z, eind none 2 jmp k jump pc ? k none 3 rcall k relative call subroutine pc ? pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 / 3 (1)
57 xmega d3 [datasheet] 8134m?avr?08/2013 eicall extended indirect call to (z) pc(15:0) pc(21:16) ? ? z, eind none 3 (1) call k call subroutine pc ? k none 3 / 4 (1) ret subroutine return pc ? stack none 4 / 5 (1) reti interrupt return pc ? stack i 4 / 5 (1) cpse rd, rr compare, skip if equal if (rd = rr) pc ? pc + 2 or 3 none 1 / 2 / 3 cp rd, rr compare rd - rr z,c,n,v,s,h 1 cpc rd, rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd, k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc ? pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc ? pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc ? pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc ? pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n ? v= 1) then pc ? pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc ? pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc ? pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd ? rr none 1 movw rd, rr copy register pair rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? k none 1 lds rd, k load direct from data space rd ? (k) none 2 (1)(2) ld rd, x load indirect rd ? (x) none 1 (1)(2) mnemonics operands description operation flags #clocks
58 xmega d3 [datasheet] 8134m?avr?08/2013 ld rd, x+ load indirect and post-increment rd x ? ? (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x ? x - 1, rd ? (x) ? ? x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd ? (y) ? (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y ? ? (y) y + 1 none 1 (1)(2) ld rd, -y load indirect and pre-decrement y rd ? ? y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd ? (y + q) none 2 (1)(2) ld rd, z load indirect rd ? (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z ? ? (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd ? ? z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) ? rd none 2 (1) st x, rr store indirect (x) ? rr none 1 (1) st x+, rr store indirect and post-increment (x) x ? ? rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) ? ? x - 1, rr none 2 (1) st y, r r store indirect (y) ? rr none 1 (1) st y+, rr store indirect and post-increment (y) y ? ? rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) ? ? y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) ? rr none 2 (1) st z, rr store indirect (z) ? rr none 1 (1) st z+, rr store indirect and post-increment (z) z ? ? rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z ? z - 1 none 2 (1) std z+q, rr store indirect with displacement (z + q) ? rr none 2 (1) lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-increment rd z ? ? (z), z + 1 none 3 elpm extended load program memory r0 ? (rampz:z) none 3 elpm rd, z extended load program memory rd ? (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z ? ? (rampz:z), z + 1 none 3 spm store program memory (rampz:z) ? r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z ? ? r1:r0, z + 2 none - in rd, a in from i/o location rd ? i/o(a) none 1 out a, rr out to i/o location i/o(a) ? rr none 1 mnemonics operands description operation flags #clocks
59 xmega d3 [datasheet] 8134m?avr?08/2013 push rr push register on stack stack ? rr none 1 (1) pop rd pop register from stack rd ? stack none 2 (1) bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c ? ? ? rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c ? ? ? rd(n+1), 0, rd(0) z,c,n,v 1 rol rd rotate left through carry rd(0) rd(n+1) c ? ? ? c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c ? ? ? c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 sbi a, b set bit in i/o register i/o(a, b) ? 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) ? 0 none 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? t none 1 sec set carry c ? 1 c 1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1 n 1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1 z 1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1 i 1 cli global interrupt disable i ? 0 i 1 ses set signed test flag s ? 1 s 1 cls clear signed test flag s ? 0 s 1 sev set two?s complement overflow v ? 1 v 1 clv clear two?s complement overflow v ? 0 v 1 set set t in sreg t ? 1 t 1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1 h 1 clh clear half carry flag in sreg h ? 0 h 1 mcu control instructions break break (see specific descr. for break) none 1 mnemonics operands description operation flags #clocks
60 xmega d3 [datasheet] 8134m?avr?08/2013 notes: 1. cycle times for data memo ry accesses assume internal memory accesses, and are not valid for accesses via the external r am interface. 2. one extra cycle must be added when accessing internal sram. nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
61 xmega d3 [datasheet] 8134m?avr?08/2013 31. packaging information 31.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. rev. 64a, 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
62 xmega d3 [datasheet] 8134m?avr?08/2013 31.2 64m
63 xmega d3 [datasheet] 8134m?avr?08/2013 32. electrical characteristics all typical values are measured at t = 25 ? c unless other temperature condition is given. all minimum and maximum values are valid across operating temperatur e and voltage unless other conditions are given. 32.1 atmel atxmega32d3 32.1.1 absolute maximum ratings stresses beyond those listed in table 32-30 on page 82 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not impli ed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 32-1. absolute maximum ratings. 32.1.2 general operating ratings the device must operate within the ratings listed in table 32-31 on page 82 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-2. general operating conditions. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105
64 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-3. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-8 on page 83 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 32-1. maximum frequency vs. v cc . symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
65 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.3 current consumption table 32-4. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 50 a v cc = 3.0v 130 1mhz, ext. clk v cc = 1.8v 215 v cc = 3.0v 475 2mhz, ext. clk v cc = 1.8v 445 600 v cc = 3.0v 0.95 1.5 ma 32mhz, ext. clk 7.8 12.0 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.8 a v cc = 3.0v 3 1mhz, ext. clk v cc = 1.8v 46 v cc = 3.0v 92 2mhz, ext. clk v cc = 1.8v 93 225 v cc = 3.0v 184 350 32mhz, ext. clk 2.9 5.0 ma power-down power consumption t=25c v cc = 3.0v 0.07 1.0 a t=85c 1.3 5.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.3 2.0 wdt and sampled bod enabled, t = 85c 2.6 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.7 v cc = 3.0v 1.8 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.5 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3.0 v cc = 3.0v 1.2 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 120
66 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-5. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.9 a 32.768khz int. oscillator 29 2mhz int. oscillator 82 dfll enabled with 32.768khz int. osc. as reference 114 32mhz int. oscillator 250 dfll enabled with 32.768khz int. osc. as reference 400 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 300 watchdog timer 1.0 bod continuous mode 140 sampled mode, includes ulp oscillator 1.4 internal 1.0v reference 180 temperature sensor 175 adc 200ksps v ref = ext. ref. 1.23 ma currlimit = low 1.1 currlimit = medium 0.98 currlimit = high 0.87 75ksps v ref = ext. ref. currlimit = low 1.7 300ksps v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 9.7 a flash memory and eeprom programming 5 ma
67 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.4 wake-up time from sleep modes table 32-6. device wake-up time from sleep modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 32-9 on page 86 . all peripherals and modules start execution from the first clock cycle, expect the cp u that is halted for four clock cycles before program executio n starts. figure 32-2. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 125 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.6 32.768khz internal oscillator 330 2mhz internal oscillator 9.5 32mhz internal oscillator 5.6 wakeup request clock output wakeup time
68 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.5 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 32-7. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1 a r p pull/buss keeper resistor 25 k ?
69 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.6 adc characteristics table 32-8. power supply, reference and input range. table 32-9. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time configurable in steps of 1/2 clk adc cycle up to 32 clk adc cycles 0.28 320 s conversion time (latency) (res+2)/2 + 1 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7
70 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-10. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbe rs are valid under the condition that external vref is used. symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.3 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
71 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-11. gain stage characteristics. 32.1.7 analog comparator characteristics table 32-12. analog comparator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock frequency same as adc 100 1800 khz gain error 0.5 gain, normal mode -1 % 1 gain, normal mode -1 8 gain, normal mode -1 64 gain, normal mode 5 offset error, input referred 0.5 gain, normal mode 10 mv 1 gain, normal mode 5 8 gain, normal mode -20 64 gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 40 ns v cc = 3.0v 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a
72 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.8 bandgap and internal 1.0v reference characteristics table 32-13. bandgap and internal 1.0v reference characteristics. 32.1.9 brownout detection characteristics table 32-14. brownout dete ction characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.1.10 external reset characteristics table 32-15. external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1 1.01 variation over voltage and temperature calibrated at t = 85c 1 % symbol parameter (bod level 0 at 85c) condition min. typ. max. units v bot bod level 0 falling v cc 1.40 1.60 1.70 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 90 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.42 * v cc r rst reset pin pull-up resistor 25 k ?
73 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.11 power-on reset characteristics table 32-16. power-on re set characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.1.12 flash and eeprom memory characteristics table 32-17. endurance and data retention. table 32-18. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 32kb flash, eeprom 50 ms application erase section erase 6 flash page erase 4 page write 4 atomic page erase and write 8 eeprom page erase 4 page write 4 atomic page erase and write 8
74 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.13 clock and osci llator characteristics 32.1.13.1 calibrated 32.768khz internal oscillator characteristics table 32-19. 32.768khz internal oscillator characteristics. 32.1.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-20. 2mhz internal oscillator characteristics. 32.1.13.3 calibrated 32mhz internal oscillator characteristics table 32-21. 32mhz internal oscillator characteristics. 32.1.13.4 32khz internal ulp oscillator characteristics table 32-22. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.18 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.19 symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibration accuracy t = 85c, v cc = 3.0v -12 12 % accuracy -30 30
75 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.13.5 internal phase locked loop (pll) characteristics table 32-23. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.1.13.6 external clock characteristics figure 32-3. external clock drive waveform. table 32-24. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
76 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-25. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.1.13.7 external 16mhz crystal o scillator and xosc characteristics table 32-26. external 16mhz crystal os cillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 0 ns frqrange=1, 2, or 3 0 xoscpwr=1 0 long term jitter xoscpwr=0 frqrange=0 0 frqrange=1, 2, or 3 0 xoscpwr=1 0 frequency error xoscpwr=0 frqrange=0 0.03 % frqrange=1 0.03 frqrange=2 or 3 0.03 xoscpwr=1 0.003 duty cycle xoscpwr=0 frqrange=0 50 frqrange=1 50 frqrange=2 or 3 50 xoscpwr=1 50
77 xmega d3 [datasheet] 8134m?avr?08/2013 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 44k ? 1mhz crystal, cl=20pf 67k 2mhz crystal, cl=20pf 67k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 82k 8mhz crystal 1500 9mhz crystal 1500 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 2700 9mhz crystal 2700 12mhz crystal 1000 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 3600 12mhz crystal 1300 16mhz crystal 590 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 390 12mhz crystal 50 16mhz crystal 10 r q negative impedance (1) xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 1500 12mhz crystal 650 16mhz crystal 270 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 1000 16mhz crystal 440 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 1300 16mhz crystal 590 esr sf = safety factor min(r q )/sf k ? start-up time xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 1.0 ms xoscpwr=0, frqrange=1 2mhz crystal, cl=20pf 2.6 xoscpwr=0, frqrange=2 8mhz crystal, cl=20pf 0.8 xoscpwr=0, frqrange=3 12mhz crystal, cl=20pf 1.0 xoscpwr=1, frqrange=3 16mhz crystal, cl=20pf 1.4 symbol parameter condition min. typ. max. units
78 xmega d3 [datasheet] 8134m?avr?08/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.1.13.8 external 32.768khz crystal osci llator and tosc characteristics table 32-27. external 32.768khz crystal o scillator and tosc characteristics. note: see figure 32-11 on page 96 for definition. figure 32-4. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. c xtal1 parasitic capacitance xtal1 pin 5.9 pf c xtal2 parasitic capacitance xtal2 pin 8.3 c load parasitic capacitance load 3.5 symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3 symbol parameter condition min. typ. max. units c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
79 xmega d3 [datasheet] 8134m?avr?08/2013 32.1.14 spi characteristics figure 32-5. spi timing requirements in master mode. figure 32-6. spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
80 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-28. spi timing characteristics and requirements. 32.1.15 two-wire interface characteristics table 32-29 on page 81 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 32-7 . figure 32-7. two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
81 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-29. two-wire interface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
82 xmega d3 [datasheet] 8134m?avr?08/2013 32.2 atmel atxmega64d3 32.2.1 absolute maximum ratings stresses beyond those listed in table 32-30 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. table 32-30. absolute maximum ratings. 32.2.2 general operating ratings the device must operate within the ratings listed in table 32-31 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-31. general operating conditions. table 32-32. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-8 on page 83 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
83 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-8. maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
84 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.3 current consumption table 32-33. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 50 a v cc = 3.0v 130 1mhz, ext. clk v cc = 1.8v 215 v cc = 3.0v 475 2mhz, ext. clk v cc = 1.8v 445 600 v cc = 3.0v 0.95 1.5 ma 32mhz, ext. clk 7.8 12.0 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.8 a v cc = 3.0v 3 1mhz, ext. clk v cc = 1.8v 46 v cc = 3.0v 92 2mhz, ext. clk v cc = 1.8v 93 225 v cc = 3.0v 184 350 32mhz, ext. clk 2.9 5.0 ma power-down power consumption t=25c v cc = 3.0v 0.07 1.0 a t=85c 1.3 5.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.3 2.0 wdt and sampled bod enabled, t = 85c 2.6 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.7 v cc = 3.0v 1.8 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.5 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3.0 v cc = 3.0v 1.2 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 120
85 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-34. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.9 a 32.768khz int. oscillator 29 2mhz int. oscillator 82 dfll enabled with 32.768khz int. osc. as reference 114 32mhz int. oscillator 250 dfll enabled with 32.768khz int. osc. as reference 400 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 300 watchdog timer 1.0 bod continuous mode 140 sampled mode, includes ulp oscillator 1.4 internal 1.0v reference 180 temperature sensor 175 adc 200ksps v ref = ext. ref. 1.23 ma currlimit = low 1.1 currlimit = medium 0.98 currlimit = high 0.87 75ksps v ref = ext. ref. currlimit = low 1.7 300ksps v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 9.7 a flash memory and eeprom programming 5 ma
86 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.4 wake-up time from sleep modes table 32-35. device wake-up time from sleep modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 32-9 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 32-9. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 125 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.6 32.768khz internal oscillator 330 2mhz internal oscillator 9.5 32mhz internal oscillator 5.6 wakeup request clock output wakeup time
87 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.5 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 32-36. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1 a r p pull/buss keeper resistor 25 k ?
88 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.6 adc characteristics table 32-37. power supply, reference and input range. table 32-38. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time configurable in steps of 1/2 clk adc cycle up to 32 clk adc cycles 0.28 320 s conversion time (latency) (res+2)/2 + 1 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7
89 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-39. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external vref is used. symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.3 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
90 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-40. gain stage characteristics. 32.2.7 analog comparator characteristics table 32-41. analog comparator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock frequency same as adc 100 1800 khz gain error 0.5 gain, normal mode -1 % 1 gain, normal mode -1 8 gain, normal mode -1 64 gain, normal mode 5 offset error, input referred 0.5 gain, normal mode 10 mv 1 gain, normal mode 5 8 gain, normal mode -20 64 gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 40 ns v cc = 3.0v 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a
91 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.8 bandgap and internal 1.0v reference characteristics table 32-42. bandgap and internal 1.0v reference characteristics. 32.2.9 brownout detection characteristics table 32-43. brownout dete ction characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.2.10 external reset characteristics table 32-44. external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1 1.01 variation over voltage and temperature calibrated at t = 85c 1 % symbol parameter (bod level 0 at 85c) condition min. typ. max. units v bot bod level 0 falling v cc 1.40 1.60 1.70 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 90 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.42 * v cc r rst reset pin pull-up resistor 25 k ?
92 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.11 power-on reset characteristics table 32-45. power-on re set characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.2.12 flash and eeprom memory characteristics table 32-46. endurance and data retention. table 32-47. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 64kb flash, eeprom 55 ms application erase section erase 6 flash page erase 4 page write 4 atomic page erase and write 8 eeprom page erase 4 page write 4 atomic page erase and write 8
93 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.13 clock and osci llator characteristics 32.2.13.1 calibrated 32.768khz internal oscillator characteristics table 32-48. 32.768khz internal oscillator characteristics. 32.2.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-49. 2mhz internal oscillator characteristics. 32.2.13.3 calibrated 32mhz internal oscillator characteristics table 32-50. 32mhz internal oscillator characteristics. 32.2.13.4 32khz internal ulp oscillator characteristics table 32-51. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.18 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.19 symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibration accuracy t = 85c, v cc = 3.0v -12 12 % accuracy -30 30
94 xmega d3 [datasheet] 8134m?avr?08/2013 32.2.13.5 internal phase locked loop (pll) characteristics table 32-52. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.2.13.6 external clock characteristics figure 32-10.external clock drive waveform. table 32-53. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
95 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-54. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.2.13.7 external 32.768khz crystal osci llator and tosc characteristics table 32-55. external 32.768khz crystal o scillator and tosc characteristics. note: see figure 32-11 for definition. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3
96 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-11.tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. 32.2.14 spi characteristics figure 32-12.spi timing requirements in master mode. figure 32-13.spi timing requirements in slave mode. c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
97 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-56. spi timing characteristics and requirements. 32.2.15 two-wire interface characteristics table 32-57 on page 98 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 32-14 on page 97 . figure 32-14.two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
98 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-57. two-wire interface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
99 xmega d3 [datasheet] 8134m?avr?08/2013 32.3 atmel atxmega128d3 32.3.1 absolute maximum ratings stresses beyond those listed in table 32-58 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. table 32-58. absolute maximum ratings. 32.3.2 general operating ratings the device must operate within the ratings listed in table 32-59 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-59. general operating conditions. table 32-60. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-15 on page 100 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
100 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-15.maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
101 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.3 current consumption table 32-61. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 55 a v cc = 3.0v 135 1mhz, ext. clk v cc = 1.8v 237 v cc = 3.0v 515 2mhz, ext. clk v cc = 1.8v 425 700 v cc = 3.0v 0.9 1.5 ma 32mhz, ext. clk 8.3 12 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.8 a v cc = 3.0v 3.1 1mhz, ext. clk v cc = 1.8v 47 v cc = 3.0v 95 2mhz, ext. clk v cc = 1.8v 94 200 v cc = 3.0v 190 400 32mhz, ext. clk 3.0 7.0 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 1.9 4.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.5 2.0 wdt and sampled bod enabled, t = 85c 3.0 8.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.3 v cc = 3.0v 1.4 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.7 2.0 v cc = 3.0v 0.8 2.0 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3.0 v cc = 3.0v 1.1 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 145
102 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-62. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.9 a 32.768khz int. oscillator 26 2mhz int. oscillator 79 dfll enabled with 32.768khz int. osc. as reference 110 32mhz int. oscillator 245 dfll enabled with 32.768khz int. osc. as reference 415 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 305 watchdog timer 1.0 bod continuous mode 138 sampled mode, includes ulp oscillator 1.4 internal 1.0v reference 185 temperature sensor 173 adc 16ksps v ref = ext. ref. 1.3 ma currlimit = low 1.15 currlimit = medium 1.0 currlimit = high 0.9 75ksps v ref = ext. ref. currlimit = low 1.7 300ksps v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 7.5 a flash memory and eeprom programming 4 ma
103 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.4 wake-up time from sleep modes table 32-63. device wake-up time from sleep modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 32-16 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 32-16.wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 130 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
104 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.5 i/o pin characteristics the i/o pins compiles with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits or exceeds this specification. table 32-64. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1.0 a r p pull/buss keeper resistor 25 k ?
105 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.6 adc characteristics table 32-65. power supply, reference and input range. table 32-66. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 ksps currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time 1/2 clk adc cycle 0.28 320 s conversion time (latency) (res+2)/2 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7
106 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-67. accuracy characteristics. notes: 1. maximum numbers are based on characterization and not test ed in production and valid for 5% to 95% input voltage range. 2. unless otherwise noted all linearity, offset and gain error numbe rs are valid under the condition that external vref is used. symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1.0 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 lsb 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.3 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3.0v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
107 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-68. gain stage characteristics. 32.3.7 analog comparator characteristics table 32-69. analog comparator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock frequency same as adc 100 1800 khz gain error 0.5x gain, normal mode -1 % 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 offset error, input referred 0.5x gain, normal mode 10 mv 1x gain, normal mode 5 8x gain, normal mode -20 64x gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 90 ns v cc = 3.0v 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accura cy after calibration 5 % current source calibration range single mode 4 6 a
108 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.8 bandgap and internal 1.0v reference characteristics table 32-70. bandgap and internal 1.0v reference characteristics. 32.3.9 brownout detection characteristics table 32-71. brownout dete ction characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.3.10 external reset characteristics table 32-72. external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1.0 1.01 variation over voltage and temperature calibrated at t = 85c 1 % symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.40 1.60 1.70 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 100 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.45 * v cc r rst reset pin pull-up resistor 27 k ?
109 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.11 power-on reset characteristics table 32-73. power-on re set characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.3.12 flash and eeprom memory characteristics table 32-74. endurance and data retention. table 32-75. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 128kb flash, eeprom 75 ms application erase section erase 6 flash page erase 4 page write 4 atomic page erase and write 8 eeprom page erase 4 page write 4 atomic page erase and write 8
110 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.13 clock and osci llator characteristics 32.3.13.1 calibrated 32.768khz internal oscillator characteristics table 32-76. 32.768khz internal oscillator characteristics. 32.3.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-77. 2mhz internal oscillator characteristics. 32.3.13.3 calibrated 32mhz internal oscillator characteristics table 32-78. 32mhz internal oscillator characteristics. 32.3.13.4 32khz internal ulp oscillator characteristics table 32-79. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.18 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.2 symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibration accuracy t = 85c, v cc = 3.0v -12 12 % accuracy -30 30
111 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.13.5 internal phase locked loop (pll) characteristics table 32-80. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.3.13.6 external clock characteristics figure 32-17.external clock drive waveform. table 32-81. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
112 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-82. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.3.13.7 external 16mhz crystal osci llator and xosc characteristics table 32-83. external 16mhz crystal oscillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 0 ns frqrange=0 0 xoscpwr=1 0 long term jitter xoscpwr=0 frqrange=0 0 frqrange=0 0 xoscpwr=1 0 frequency error xoscpwr=0 frqrange=0 0.03 % frqrange=0 0.03 frqrange=0 0.03 xoscpwr=1 0.003 duty cycle xoscpwr=0 frqrange=0 50 frqrange=0 50 frqrange=0 50 xoscpwr=1 50
113 xmega d3 [datasheet] 8134m?avr?08/2013 negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 44k ? r q 1mhz resonator, cl=20pf 67k 2mhz resonator, cl=20pf 67k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 82k 8mhz crystal 1500 9mhz crystal 1500 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 2700 9mhz crystal 2700 12mhz crystal 1000 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 3600 12mhz crystal 1300 16mhz crystal 590 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 390 12mhz crystal 50 16mhz crystal 10 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 1500 12mhz crystal 650 16mhz crystal 270 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 1000 16mhz crystal 440 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 1300 16mhz crystal 590 esr sf = safety factor min(r q )/sf k ? start-up time xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 1.0 ms xoscpwr=0, frqrange=1 2mhz crystal, cl=20pf 2.6 xoscpwr=0, frqrange=2 8mhz crystal, cl=20pf 0.8 xoscpwr=0, frqrange=3 12mhz crystal, cl=20pf 1.0 xoscpwr=1, frqrange=3 16mhz crystal, cl=20pf 1.4 symbol parameter condition min. typ. max. units
114 xmega d3 [datasheet] 8134m?avr?08/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.3.13.8 external 32.768khz crystal osci llator and tosc characteristics table 32-84. external 32.768khz crystal o scillator and tosc characteristics. note: see figure 32-18 for definition. figure 32-18.tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. c xtal1 parasitic capacitance xtal1 pin 5.9 pf c xtal2 parasitic capacitance xtal1 pin 8.3 c load parasitic capacitance load 3.5 symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3 symbol parameter condition min. typ. max. units c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
115 xmega d3 [datasheet] 8134m?avr?08/2013 32.3.14 spi characteristics figure 32-19.spi timing requirements in master mode. figure 32-20.spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
116 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-85. spi timing characteristics and requirements. 32.3.15 two-wire interface characteristics table 32-86 on page 117 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds thes e requirements under the noted conditions. timing symbols refer to figure 32-21 . figure 32-21.two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
117 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-86. two-wire interface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
118 xmega d3 [datasheet] 8134m?avr?08/2013 32.4 atmel atxmega192d3 32.4.1 absolute maximum ratings stresses beyond those listed in table 32-87 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. table 32-87. absolute maximum ratings. 32.4.2 general operating ratings the device must operate within the ratings listed in table 32-88 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-88. general operating conditions. table 32-89. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-22 on page 119 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
119 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-22.maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
120 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.3 current consumption table 32-90. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set including fprm and eprm. 2. all power reduction registers set without fprm and eprm. 3. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 60 a v cc = 3.0v 140 1mhz, ext. clk v cc = 1.8v 245 v cc = 3.0v 550 2mhz, ext. clk v cc = 1.8v 440 700 v cc = 3.0v 0.9 1.5 ma 32mhz, ext. clk 9.0 15 idle power consumption (2) 32khz, ext. clk v cc = 1.8v 3.0 a v cc = 3.0v 3.5 1mhz, ext. clk v cc = 1.8v 55 v cc = 3.0v 110 2mhz, ext. clk v cc = 1.8v 105 350 v cc = 3.0v 215 650 32mhz, ext. clk 3.4 8.0 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 3.5 6.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.5 2.0 wdt and sampled bod enabled, t = 85c 5.8 10 power-save power consumption (3) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.3 v cc = 3.0v 1.4 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.7 2.0 v cc = 3.0v 0.8 2.0 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3.0 v cc = 3.0v 1.1 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 170
121 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-91. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.9 a 32.768khz int. oscillator 25 2mhz int. oscillator 78 dfll enabled with 32.768khz int. osc. as reference 110 32mhz int. oscillator 250 dfll enabled with 32.768khz int. osc. as reference 440 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 310 watchdog timer 1.0 bod continuous mode 132 sampled mode, includes ulp oscillator 1.4 internal 1.0v reference 185 temperature sensor 182 adc 16ksps v ref = ext. ref. 1.12 ma currlimit = low 1.01 currlimit = medium 0.9 currlimit = high 0.8 75ksps v ref = ext. ref. currlimit = low 1.7 300ksps, v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 9.5 a flash memory and eeprom programming 10 ma
122 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.4 wake-up time from sleep modes table 32-92. device wake-up time from sleep modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 32-23 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 32-23.wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 125 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.6 32.768khz internal oscillator 330 2mhz internal oscillator 9.5 32mhz internal oscillator 5.6 wakeup request clock output wakeup time
123 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.5 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 32-93. i/o pi n characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1.0 a r p pull/buss keeper resistor 25 k ?
124 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.6 adc characteristics table 32-94. power supply, reference and input range. table 32-95. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time configurable in steps of 1/2 clk adc cycles up to 32 clk adc cycles 0.28 320 s conversion time (latency) (res+2)/2 + 1 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7
125 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-96. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset, and gain error num bers are valid under the condition that external vref is used . symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.3 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3.0v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
126 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-97. gain stage characteristics. 32.4.7 analog comparator characteristics table 32-98. analog comparator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock frequency same as adc 100 1800 khz gain error 0.5 gain, normal mode -1 % 1 gain, normal mode -1 8 gain, normal mode -1 64 gain, normal mode 5 offset error, input referred 0.5 gain, normal mode 10 mv 1 gain, normal mode 5 8 gain, normal mode -20 64 gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 40 ns v cc = 3.0v 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a
127 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.8 bandgap and internal 1.0v reference characteristics table 32-99. bandgap and internal 1.0v reference characteristics. 32.4.9 brownout detection characteristics table 32-100.brownout detection characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.4.10 external reset characteristics table 32-101.external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1.0 1.01 variation over voltage and temperature calibrated at t = 85c 1 % symbol parameter (bod level 0 at 85c) condition min. typ. max. units v bot bod level 0 falling v cc 1.40 1.60 1.70 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 90 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.45 * v cc r rst reset pin pull-up resistor 25 k ?
128 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.11 power-on reset characteristics table 32-102.power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.4.12 flash and eeprom memory characteristics table 32-103.endurance and data retention. table 32-104. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 192kb flash, eeprom 90 ms application erase section erase 6 flash page erase 4 page write 4 atomic page erase and write 8 eeprom page erase 4 page write 4 atomic page erase and write 8
129 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.13 clock and osci llator characteristics 32.4.13.1 calibrated 32.768khz internal oscillator characteristics table 32-105. 32.768khz internal oscillator characteristics. 32.4.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-106. 2mhz internal oscillator characteristics. 32.4.13.3 calibrated 32mhz internal oscillator characteristics table 32-107. 32mhz internal oscillator characteristics. 32.4.13.4 32khz internal ulp oscillator characteristics table 32-108. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.18 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.19 symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -12 12 % accuracy -30 30
130 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.13.5 internal phase locked loop (pll) characteristics table 32-109. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.4.13.6 external clock characteristics figure 32-24. external clock drive waveform. table 32-110.external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
131 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-111.external cl ock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.4.13.7 external 16mhz crystal osci llator and xosc characteristics table 32-112. external 16mhz crystal o scillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 0 ns frqrange=1, 2, or 3 0 xoscpwr=1 0 long term jitter xoscpwr=0 frqrange=0 0 frqrange=1, 2, or 3 0 xoscpwr=1 0 frequency error xoscpwr=0 frqrange=0 0.03 % frqrange=1 0.03 frqrange=2 or 3 0.03 xoscpwr=1 0.003 duty cycle xoscpwr=0 frqrange=0 50 frqrange=1 50 frqrange=2 or 3 50 xoscpwr=1 50
132 xmega d3 [datasheet] 8134m?avr?08/2013 notes: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 44k ? 1mhz crystal, cl=20pf 67k 2mhz crystal, cl=20pf 67k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 82k 8mhz crystal 1500 9mhz crystal 1500 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 2700 9mhz crystal 2700 12mhz crystal 1000 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 3600 12mhz crystal 1300 16mhz crystal 590 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 390 12mhz crystal 50 16mhz crystal 10 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 1500 12mhz crystal 650 16mhz crystal 270 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 1000 16mhz crystal 440 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 1300 16mhz crystal 590 ms start-up time xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 1.0 xoscpwr=0, frqrange=1 2mhz resonator, cl=20pf 2.6 xoscpwr=0, frqrange=2 8mhz resonator, cl=20pf 0.8 xoscpwr=0, frqrange=3 12mhz resonator, cl=20pf 1.0 xoscpwr=1, frqrange=3 16mhz resonator, cl=20pf 1.4 c xtal1 parasitic capacitance xtal1 pin 5.9 pf c xtal2 parasitic capacitance xtal2 pin 8.3 c load paracitic capacitance load 3.5 symbol parameter condition min. typ. max. units
133 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.13.8 external 32.768khz crystal osci llator and tosc characteristics table 32-113. external 32.768khz crystal oscillator and tosc characteristics. note: see figure 32-25 for definition. figure 32-25. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
134 xmega d3 [datasheet] 8134m?avr?08/2013 32.4.14 spi characteristics figure 32-26. spi timing requirements in master mode. figure 32-27. spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
135 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-114. spi timing characteristics and requirements. 32.4.15 two-wire interface characteristics table 32-115 on page 136 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds thes e requirements under the noted conditions. timing symbols refer to figure 32-28 . figure 32-28. two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
136 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-115. two-wire in terface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
137 xmega d3 [datasheet] 8134m?avr?08/2013 32.5 atmel atxmega256d3 32.5.1 absolute maximum ratings stresses beyond those listed in table 32-116 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. table 32-116. absolute maximum ratings. 32.5.2 general operating ratings the device must operate within the ratings listed in table 32-117 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-117. general operating conditions. table 32-118. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-29 on page 138 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
138 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-29. maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
139 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.3 current consumption table 32-119. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set including fprm and eprm. 2. all power reduction registers set without fprm and eprm. 3. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 60 a v cc = 3.0v 140 1mhz, ext. clk v cc = 1.8v 245 v cc = 3.0v 550 2mhz, ext. clk v cc = 1.8v 440 700 v cc = 3.0v 0.9 1.5 ma 32mhz, ext. clk 9.0 15 idle power consumption (2) 32khz, ext. clk v cc = 1.8v 3.0 a v cc = 3.0v 3.5 1mhz, ext. clk v cc = 1.8v 55 v cc = 3.0v 110 2mhz, ext. clk v cc = 1.8v 105 350 v cc = 3.0v 215 650 32mhz, ext. clk 3.4 8.0 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 3.5 6.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.5 2.0 wdt and sampled bod enabled, t = 85c 5.8 10 power-save power consumption (3) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.3 v cc = 3.0v 1.4 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.7 2.0 v cc = 3.0v 0.8 2.0 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3.0 v cc = 3.0v 1.1 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 170
140 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-120. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.9 a 32.768khz int. oscillator 25 2mhz int. oscillator 78 dfll enabled with 32.768khz int. osc. as reference 110 32mhz int. oscillator 250 dfll enabled with 32.768khz int. osc. as reference 440 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 310 watchdog timer 1.0 bod continuous mode 132 sampled mode, includes ulp oscillator 1.4 internal 1.0v reference 185 temperature sensor 182 adc 16ksps v ref = ext. ref. 1.12 ma currlimit = low 1.01 currlimit = medium 0.9 currlimit = high 0.8 75ksps v ref = ext. ref. currlimit = low 1.7 300ksps v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 9.5 a flash memory and eeprom programming 10 ma
141 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.4 wake-up time from sleep modes table 32-121. device wake-up time from slee p modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 32-30 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 32-30. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 125 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.6 32.768khz internal oscillator 330 2mhz internal oscillator 9.5 32mhz internal oscillator 5.6 wakeup request clock output wakeup time
142 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.5 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 32-122. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1.0 a r p pull/buss keeper resistor 25 k ?
143 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.6 adc characteristics table 32-123. power supply, reference and input range. table 32-124. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time configurable in steps of 1/2 clk adc cycles up to 32 clk adc cycles 0.28 320 s conversion time (latency) (res+2)/2 + 1 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7
144 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-125. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset, and gain error num bers are valid under the condition that external vref is used . symbol parameter condition (2) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (1) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (1) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.3 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3.0v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
145 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-126. gain stage characteristics. 32.5.7 analog comparator characteristics table 32-127. analog compar ator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock frequency same as adc 100 1800 khz gain error 0.5 gain, normal mode -1 % 1 gain, normal mode -1 8 gain, normal mode -1 64 gain, normal mode 5 offset error, input referred 0.5 gain, normal mode 10 mv 1 gain, normal mode 5 8 gain, normal mode -20 64 gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 40 ns v cc = 3.0v 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range single mode 4 6 a
146 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.8 bandgap and internal 1.0v reference characteristics table 32-128. bandgap and internal 1.0v reference characteristics. 32.5.9 brownout detection characteristics table 32-129. brownout detection characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.5.10 external reset characteristics table 32-130. external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1.0 1.01 variation over voltage and temperature calibrated at t = 85c 1 % symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.40 1.60 1.70 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 90 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.45 * v cc r rst reset pin pull-up resistor 25 k ?
147 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.11 power-on reset characteristics table 32-131. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.5.12 flash and eeprom memory characteristics table 32-132. endurance and data retention. table 32-133. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 100k cycle 85c 100k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 256kb flash, eeprom 105 ms application erase section erase 6 flash page erase 4 page write 4 atomic page erase and write 8 eeprom page erase 4 page write 4 atomic page erase and write 8
148 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.13 clock and osci llator characteristics 32.5.13.1 calibrated 32.768khz internal oscillator characteristics table 32-134. 32.768khz internal oscillator characteristics. 32.5.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-135. 2mhz internal oscillator characteristics. 32.5.13.3 calibrated 32mhz internal oscillator characteristics table 32-136. 32mhz internal oscillator characteristics. 32.5.13.4 32khz internal ulp oscillator characteristics table 32-137. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.18 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.19 symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -12 12 %
149 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.13.5 internal phase locked loop (pll) characteristics table 32-138. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.5.13.6 external clock characteristics figure 32-31.external clock drive waveform. table 32-139.external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
150 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-140.external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.5.13.7 external 16mhz crystal osci llator and xosc characteristics table 32-141. external 16mhz crystal o scillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 0 ns frqrange=1, 2, or 3 0 xoscpwr=1 0 long term jitter xoscpwr=0 frqrange=0 0 frqrange=1, 2, or 3 0 xoscpwr=1 0 frequency error xoscpwr=0 frqrange=0 0.03 % frqrange=1 0.03 frqrange=2 or 3 0.03 xoscpwr=1 0.003 duty cycle xoscpwr=0 frqrange=0 50 frqrange=1 50 frqrange=2 or 3 50 xoscpwr=1 50
151 xmega d3 [datasheet] 8134m?avr?08/2013 notes: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 44k ? 1mhz crystal, cl=20pf 67k 2mhz crystal, cl=20pf 67k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 82k 8mhz crystal 1500 9mhz crystal 1500 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 2700 9mhz crystal 2700 12mhz crystal 1000 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 3600 12mhz crystal 1300 16mhz crystal 590 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 390 12mhz crystal 50 16mhz crystal 10 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 1500 12mhz crystal 650 16mhz crystal 270 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 1000 16mhz crystal 440 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 1300 16mhz crystal 590 ms start-up time xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 1.0 xoscpwr=0, frqrange=1 2mhz resonator, cl=20pf 2.6 xoscpwr=0, frqrange=2 8mhz resonator, cl=20pf 0.8 xoscpwr=0, frqrange=3 12mhz resonator, cl=20pf 1.0 xoscpwr=1, frqrange=3 16mhz resonator, cl=20pf 1.4 c xtal1 parasitic capacitance xtal1 pin 5.9 pf c xtal2 parasitic capacitance xtal2 pin 8.3 c load paracitic capacitance load 3.5 symbol parameter condition min. typ. max. units
152 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.13.8 external 32.768khz crystal osci llator and tosc characteristics table 32-142. external 32.768khz crystal oscillator and tosc characteristics. note: see figure 32-32 for definition. figure 32-32. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
153 xmega d3 [datasheet] 8134m?avr?08/2013 32.5.14 spi characteristics figure 32-33. spi timing requirements in master mode. figure 32-34. spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
154 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-143. spi timing characteristics and requirements. 32.5.15 two-wire interface characteristics table 32-144 on page 155 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds thes e requirements under the noted conditions. timing symbols refer to figure 32-35 . figure 32-35. two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
155 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-144. two-wire in terface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
156 xmega d3 [datasheet] 8134m?avr?08/2013 32.6 atmel atxmega384d3 32.6.1 absolute maximum ratings stresses beyond those listed in table 32-145 under may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. table 32-145. absolute maximum ratings. 32.6.2 general operating ratings the device must operate within the ratings listed in table 32-146 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 32-146. general operating conditions. table 32-147. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 32-36 on page 157 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 v pin pin voltage with respect to gnd and v cc -0.5 v cc + 0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 t a temperature range -40 85 c t j junction temperature -40 105 symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
157 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-36. maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
158 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.3 current consumption table 32-148. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 150 a v cc = 3.0v 320 1mhz, ext. clk v cc = 1.8v 410 v cc = 3.0v 830 2mhz, ext. clk v cc = 1.8v 660 800 v cc = 3.0v 1.3 1.8 ma 32mhz, ext. clk 10 15 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 4 a v cc = 3.0v 5 1mhz, ext. clk v cc = 1.8v 50 v cc = 3.0v 100 2mhz, ext. clk v cc = 1.8v 100 350 v cc = 3.0v 200 600 32mhz, ext. clk 3.3 7 ma power-down power consumption t=25c v cc = 3.0v 0.2 1.0 a t=85c 3.5 6.0 wdt and sampled bod enabled, t = 25c v cc = 3.0v 1.5 2.0 wdt and sampled bod enabled, t = 85c 6 10 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.4 v cc = 3.0v 1.5 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.7 2 v cc = 3.0v 0.8 2 rtc from low power 32.768khz tosc, t=25c v cc = 1.8v 0.9 3 v cc = 3.0v 1.1 3 reset power consumption current through reset pin substracted v cc = 3.0v 300
159 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-149. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 0.93 a 32.768khz int. oscillator 27 2mhz int. oscillator 85 dfll enabled with 32.768khz int. osc. as reference 115 32mhz int. oscillator 240 dfll enabled with 32.768khz int. osc. as reference 430 pll 20 multiplication factor, 32mhz int. osc. div4 as reference 300 watchdog timer 1 bod continuous mode 140 sampled mode, includes ulp oscillator 1.3 internal 1.0v reference 220 temperature sensor 215 adc 16ksps, v ref = ext. ref. 1.12 ma currlimit = low 1.01 currlimit = medium 0.9 currlimit = high 0.8 75ksps, v ref = ext. ref. currlimit = low 1.7 300ksps, v ref = ext. ref. 3.1 usart rx and tx enabled, 9600 baud 9.5 a flash memory and eeprom programming 4 ma
160 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.4 wake-up time from sleep modes table 32-150. device wake-up time from slee p modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral cl ock is available on pin, see figure 32-37 on page 160 . all peripherals and modules start execution from the first clock cycle, expect the cp u that is halted for four clock cycles before program executio n starts. figure 32-37. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 130 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power- down mode external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
161 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.5 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 32-151. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc, portd, porte must for each port not exceed 200ma. the sum of all i oh for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc, portd, porte must for each port not exceed 200ma. the sum of all i ol for pins pf[0-5] on portf must not exceed 200ma. the sum of all i ol for pins pf[6-7] on portf, portr and pdi must not exceed 100ma. 32.6.6 adc characteristics table 32-152. power supply, reference and input range. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -15 15 ma v ih high level input voltage v cc = 2.4 - 3.6v 0.7 * v cc v cc + 0.5 v v cc = 1.6 - 2.4v 0.8 * v cc v cc + 0.5 v il low level input voltage v cc = 2.4 - 3.6v -0.5 0.3 * v cc v cc = 1.6 - 2.4v -0.5 0.2 * v cc v oh high level output voltage v cc = 3.3v i oh = -4ma 2.6 2.9 v cc = 3.0v i oh = -3ma 2.1 2.6 v cc = 1.8v i oh = -1ma 1.4 1.6 v ol low level output voltage v cc = 3.3v i ol = 8ma 0.4 0.76 v cc = 3.0v i ol = 5ma 0.3 0.64 v cc = 1.8v i ol = 3ma 0.2 0.46 i in input leakage current i/o pin t = 25c <0.01 1 a r p pull/buss keeper resistor 25 k ? symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 r in input resistance switched 4.5 k ? c in input capacitance switched 5 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf
162 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-153. clock and timing. v in input range 0 v ref v conversion range differential mode, vinp - vinn -v ref v ref conversion range single ended unsigned mode, vinp - ? v v ref - ? v ? v fixed offset voltage 200 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 1800 khz measuring internal signals 100 125 f clkadc sample rate 16 300 ksps f adc sample rate current limitation (currlimit) off 16 300 currlimit = low 16 250 currlimit = medium 16 150 currlimit = high 16 50 sampling time configurable in steps of 1/2 clk adc cycles up to 32 clk adc cycles 0.28 320 s conversion time (latency) (res+1)/2 + gain res (resolution) = 8 or 12, gain = 0 to 3 5.5 10 clk adc cycles start-up time adc clock cycles 12 24 adc settling time after changing reference or input mode 7 7 symbol parameter condition min. typ. max. units
163 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-154. accuracy characteristics. notes: 1. unless otherwise noted all linearity, offset and gain erro r numbers are valid under the condition that external vref is used. 2. maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. symbol parameter condition (1) min. typ. max. units res resolution 12-bit resolution differential 8 12 12 bits single ended signed 7 11 11 single ended unsigned 8 12 12 inl (2) integral non-linearity differential mode 16ksps, v ref = 3v 0.5 1 lsb 16ksps, all v ref 0.8 2 300ksps, v ref = 3v 0.6 1 300ksps, all v ref 1 2 single ended unsigned mode 16ksps, v ref = 3.0v 0.5 1 16ksps, all v ref 1.3 2 dnl (2) differential non-linearity differential mode 16ksps, v ref = 3v 0.3 1 16ksps, all v ref 0.5 1 300ksps, v ref = 3v 0.35 1 300ksps, all v ref 0.5 1 single ended unsigned mode 16ksps, v ref = 3.0v 0.6 1 16ksps, all v ref 0.6 1 offset error differential mode 300ksps, v ref = 3v -7 mv temperature drift, v ref = 3v 0.01 mv/k operating voltage drift 0.16 mv/v gain error differential mode external reference -5 mv av cc /1.6 -5 av cc /2.0 -6 bandgap 10 temperature drift 0.02 mv/k operating voltage drift 2 mv/v gain error single ended unsigned mode external reference -8 mv av cc /1.6 -8 av cc /2.0 -8 bandgap 10 temperature drift 0.03 mv/k operating voltage drift 2 mv/v
164 xmega d3 [datasheet] 8134m?avr?08/2013 table 32-155. gain stage characteristics. 32.6.7 analog comparator characteristics table 32-156. analog compar ator characteristics. symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 av cc - 0.6 v propagation delay adc conversion rate 1/2 1 3 clk adc cycles clock rate same as adc 100 1800 khz gain error 0.5x gain, normal mode -1 % 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 offset error, input referred 0.5x gain, normal mode 10 mv 1x gain, normal mode 5 8x gain, normal mode -20 64x gain, normal mode -126 symbol parameter condition min. typ. max. units v off input offset voltage 10 mv i lk input leakage current <10 50 na input voltage range -0.1 av cc v ac startup time 50 s v hys1 hysteresis, none v cc = 1.6v - 3.6v 0 mv v hys2 hysteresis, small v cc = 1.6v - 3.6v 15 v hys3 hysteresis, large v cc = 1.6v - 3.6v 30 t delay propagation delay v cc = 3.0v, t = 85c 20 90 ns v cc = 3.0v, t = 85c 17 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb current source accuracy after calibration 5 % current source calibration range 4 6 a
165 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.8 bandgap and internal 1.0v reference characteristics table 32-157. bandgap and internal 1.0v reference characteristics. 32.6.9 brownout detection characteristics table 32-158. brownout detection characteristics (1) . note: 1. bod is calibrated at 85c within bod level 0 values, and bod level 0 is the default level. 32.6.10 external reset characteristics table 32-159. external reset characteristics. symbol parameter condition min. typ. max. units startup time as reference for adc 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t = 85c, after calibration 0.99 1 1.01 variation over voltage and temperature calibrated at t = 85c 2 % symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.60 1.62 1.72 v bod level 1 falling v cc 1.9 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.0 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 90 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.45 * v cc v v cc = 1.6 - 2.7v 0.42 * v cc r rst reset pin pull-up resistor 25 k ?
166 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.11 power-on reset characteristics table 32-160. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . 32.6.12 flash and eeprom memory characteristics table 32-161. endurance and data retention. table 32-162. programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.3 v pot+ por threshold voltage rising v cc 1.3 1.59 symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase (2) 384kb flash, eeprom 130 ms application erase section erase 6 flash page erase 6 page write 6 atomic page erase and write 12 eeprom page erase 6 page write 6 atomic page erase and write 12
167 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.13 clock and osci llator characteristics 32.6.13.1 calibrated 32.768khz internal oscillator characteristics table 32-163. 32.768khz internal oscillator characteristics. 32.6.13.2 calibrated 2mhz rc inte rnal oscillator characteristics table 32-164. 2mhz internal oscillator characteristics. 32.6.13.3 calibrated 32mhz internal oscillator characteristics table 32-165. 32mhz internal oscillator characteristics. 32.6.13.4 32khz internal ulp oscillator characteristics table 32-166. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.23 symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 32 35 mhz factory calibrated frequency 32 factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.24 symbol parameter condition min. typ. max. units factory calibrated frequency 26 khz factory calibration accuracy t = 85c, v cc = 3.0v -12 12 % accuracy -30 30
168 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.13.5 internal phase locked loop (pll) characteristics table 32-167. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 32.6.13.6 external clock characteristics figure 32-38. external clock drive waveform. table 32-168.external clock used as system clock without prescaling. symbol parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
169 xmega d3 [datasheet] 8134m?avr?08/2013 note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. table 32-169.external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 32.6.13.7 external 32.768khz crystal osci llator and tosc characteristics table 32-170. external 32.768khz crystal oscillator and tosc characteristics. note: see figure 32-39 for definition. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 crystal load capacitance 12pf 28 c tosc1 parasitic capacitance tosc1 pin 3.5 pf c tosc2 parasitic capacitance tosc2 pin 3.5 recommended safety factor capacitance load matched to crystal specification 3
170 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-39. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. 32.6.14 spi characteristics figure 32-40. spi timing requirements in master mode. c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss
171 xmega d3 [datasheet] 8134m?avr?08/2013 figure 32-41. spi timing requirements in slave mode. table 32-171. spi timing characteristics and requirements. msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss symbol parameter condition min. typ. max. units t sck sck period master (see table 20-3 in xmega d manual ) ns t sckw sck high/low width master 0.5 * sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5 * sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4 * t clk per t ssckw sck high/low width slave 2 * t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8
172 xmega d3 [datasheet] 8134m?avr?08/2013 32.6.15 two-wire interface characteristics table 32-172 on page 172 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds thes e requirements under the noted conditions. timing symbols refer to figure 32-42 . figure 32-42. two-wire interface bus timing. table 32-172. two-wire in terface characteristics. t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20 + 0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) > max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 f scl > 100khz 0.6 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
173 xmega d3 [datasheet] 8134m?avr?08/2013 notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 f scl > 100khz 1.3 symbol parameter condition min. typ. max. units
174 xmega d3 [datasheet] 8134m?avr?08/2013 33. typical characteristics 33.1 atmel atxmega32d3 33.1.1 active su pply current figure 33-1. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-2. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 0 100 200 300 400 500 600 700 800 900 frequency [mhz] i cc [a] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3.3v 3.0v 2.7v 0 2 4 6 8 10 12 14 16 18 20 0 4 8 121620242832 frequency [mhz] i cc [ma] 2.2v 1.8v
175 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-3. active supply current vs. v cc . f sys = 1.0mhz external clock . figure 33-4. active supply current vs. v cc . f sys = 32.768khz internal rc . 85c 25c -40c 0 100 200 300 400 500 600 700 800 900 1000 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 20 40 60 80 100 120 140 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
176 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-5. active supply current vs. v cc . f sys = 2.0mhz internal rc . figure 33-6. active supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz. 85c 25c -40c 0 200 400 600 800 1000 1200 1400 1600 1800 2000 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 1 2 3 4 5 6 7 8 v cc [v] i cc [ma] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
177 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-7. active supply current vs. v cc . f sys = 32mhz internal rc . 33.1.2 idle supply current figure 33-8. idle supply current vs. frequency. f sys = 0 - 1.0mhz, t = 25c . 85c 25c -40c 0 5 10 15 20 25 v cc [v] i cc [ma] 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.3v 3.0v 2.7v 2.2v 1.8v 0 50 100 150 200 250 frequency [mhz] i cc [a] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
178 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-9. idle supply current vs. frequency. f sys = 1 - 32mhz, t = 25c . figure 33-10. idle supply current vs. v cc . f sys = 1.0mhz external clock . 3.3v 3.0v 2.7v 0 1 2 3 4 5 6 7 8 0 4 8 12 16 20 24 28 32 frequency [mhz] i cc [ma] 1.8v 2.2v 85c 25c -40c 0 50 100 150 200 250 300 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
179 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-11. idle supply current vs. v cc . f sys = 32.768khz internal rc . figure 33-12. idle supply current vs. v cc . f sys = 2.0mhz internal rc . 85c 25c -40c 0 5 10 15 20 25 30 35 40 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 100 200 300 400 500 600 700 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
180 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-13. idle supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz . figure 33-14. idle supply current vs. v cc . f sys = 32mhz internal rc . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc [v] i cc [ma] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 2 4 6 8 10 v cc [v] i cc [ma] 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
181 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.3 power-down supply current figure 33-15. power-down supply current vs. temperature. figure 33-16. power-down supply current vs. temperature. with wdt and sampled bod enabled . 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a] 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a]
182 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.4 power-save supply current figure 33-17. power-save supply current vs. temperature. with wdt, sampled bod, and rtc from ulp enabled . 33.1.5 pin pull-up figure 33-18. reset pull-up resist or current vs. reset pin voltage. v cc = 1.8v . 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a] 85c 25c -40c 0 20 40 60 80 100 v reset [v] i reset [a] 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
183 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-19. reset pull-up resist or current vs. reset pin voltage. v cc = 3.0v . figure 33-20. reset pull-up resist or current vs. reset pin voltage. v cc = 3.3v . 85c 25c -40c 0 20 40 60 80 100 120 140 160 v reset [v] i reset [a] 0 0.5 1.0 1.5 2.0 2.5 3.0 85c 25c -40c 0 20 40 60 80 100 120 140 160 180 v reset [v] i reset [a] 0 0.5 1.0 1.5 2.0 2.5 3.0
184 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.6 pin output voltage vs. sink/source current figure 33-21. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-22. i/o pin output voltage vs. source current. v cc = 3.0v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i pin [ma] v pin [v] -6 -5 -4 -3 -2 -1 0 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i pin [ma] v pin [v] -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
185 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-23. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-24. i/o pin output voltage vs. sink current. v cc = 1.8v . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i pin [ma] v pin [v] -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i pin [ma] v pin [v] 25c 85c 0 1 2 3 4 5 6 7 8 9 10
186 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-25. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-26. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i pin [ma] v pin [v] 0 1 2 3 4 5 6 7 8 9 10 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i pin [ma] v pin [v] 0 1 2 3 4 5 6 7 8 9 10
187 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.7 thresholds and hysteresis figure 33-27. i/o pin input threshold voltage vs. v cc . v ih - i/o pin read as ?1? . figure 33-28. i/o pin input threshold voltage vs. v cc . v il - i/o pin read as ?0? . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
188 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-29. i/o pin input hysteresis vs. v cc . figure 33-30. reset input threshold voltage vs. v cc . v il - i/o pin read as ?1? . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
189 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-31. reset input threshold voltage vs. v cc . v il - i/o pin read as ?0? . 33.1.8 bod thresholds figure 33-32. bod thresholds vs. temperature. bod level = 1.6v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 rising vcc falling vcc 1.61 1.62 1.63 1.64 1.65 1.66 1.67 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] v bot [v]
190 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-33. bod thresholds vs. temperature. bod level = 2.9v . 33.1.9 oscillators and wake-up time 33.1.9.1 internal 32.768khz oscillator figure 33-34. internal 32.768khz os cillator calibration step size. t = -40 to 85c, v cc = 3v . rising vcc falling vcc 2.90 2.92 2.94 2.96 2.98 3.00 3.02 3.04 3.06 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] v bot [v] 0 32 64 96 128 160 192 224 256 rc32kcal[7..0] 0.05% 0.20% 0.35% 0.50% 0.65% 0.80% step size: f [khz]
191 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.9.2 internal 2mhz oscillator figure 33-35. internal 2mhz oscill ator cala calibration step size. t = -40 to 85c, v cc = 3v . figure 33-36. internal 2mhz oscill ator calb calibration step size. t = -40 to 85c, v cc = 3v . -0.30% -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 0.40% 0.50% 0 163248648096112128 dfllrc2mcala step size: f [mhz] 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 0 8 16 24 32 40 48 56 64 dfllrc2mcalb step size: f [mhz]
192 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.9.3 internal 32mhz oscillator figure 33-37. internal 32mhz oscillator cala calibration step size. t = -40 to 85c, v cc = 3v . figure 33-38. internal 32mhz oscillator calb calibration step size. t = -40 to 85c, v cc = 3v . -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 0.40% 0.50% 0.60% 0 163248648096112128 dfllrc32mcala step size: f [mhz] 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 0 8 16 24 32 40 48 56 64 dfllrc32mcalb step size: f [mhz]
193 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.10 module current consumption figure 33-39. ac current consumption vs. v cc . low-power mode . figure 33-40. power-up current consumption vs. v cc . 85c 25c -40c 0 20 40 60 80 100 120 v cc [v] module current consumption [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 100 200 300 400 500 600 700 v cc [v] i cc [a] 0.4 0.6 0.8 1.0 1.2 1.4 1.6
194 xmega d3 [datasheet] 8134m?avr?08/2013 33.1.11 reset pulse width figure 33-41. minimum reset pulse width vs. v cc . 33.1.12 pdi speed figure 33-42. pdi speed vs. v cc . 85c 25c -40c 0 20 40 60 80 100 120 v cc [v] t rst [ns] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 25c 0 5 10 15 20 25 30 35 v cc [v] f max [mhz] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
195 xmega d3 [datasheet] 8134m?avr?08/2013 33.2 atmel atxmega64d3 33.2.1 active su pply current figure 33-43. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-44. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 0 100 200 300 400 500 600 700 800 900 frequency [mhz] i cc [a] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3.3v 3.0v 2.7v 0 2 4 6 8 10 12 14 16 18 20 0 4 8 121620242832 frequency [mhz] i cc [ma] 2.2v 1.8v
196 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-45. active supply current vs. v cc . f sys = 1.0mhz external clock . figure 33-46. active supply current vs. v cc . f sys = 32.768khz internal rc . 85c 25c -40c 0 100 200 300 400 500 600 700 800 900 1000 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 20 40 60 80 100 120 140 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
197 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-47. active supply current vs. v cc . f sys = 2.0mhz internal rc . figure 33-48. active supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz. 85c 25c -40c 0 200 400 600 800 1000 1200 1400 1600 1800 2000 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 1 2 3 4 5 6 7 8 v cc [v] i cc [ma] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
198 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-49. active supply current vs. v cc . f sys = 32mhz internal rc . 33.2.2 idle supply current figure 33-50. idle supply current vs. frequency. f sys = 0 - 1.0mhz, t = 25c . 85c 25c -40c 0 5 10 15 20 25 v cc [v] i cc [ma] 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.3v 3.0v 2.7v 2.2v 1.8v 0 50 100 150 200 250 frequency [mhz] i cc [a] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
199 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-51. idle supply current vs. frequency. f sys = 1 - 32mhz, t = 25c . figure 33-52. idle supply current vs. v cc . f sys = 1.0mhz external clock . 3.3v 3.0v 2.7v 0 1 2 3 4 5 6 7 8 0 4 8 12 16 20 24 28 32 frequency [mhz] i cc [ma] 1.8v 2.2v 85c 25c -40c 0 50 100 150 200 250 300 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
200 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-53. idle supply current vs. v cc . f sys = 32.768khz internal rc . figure 33-54. idle supply current vs. v cc . f sys = 2.0mhz internal rc . 85c 25c -40c 0 5 10 15 20 25 30 35 40 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 100 200 300 400 500 600 700 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
201 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-55. idle supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz . figure 33-56. idle supply current vs. v cc . f sys = 32mhz internal rc . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc [v] i cc [ma] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 2 4 6 8 10 v cc [v] i cc [ma] 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
202 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.3 power-down supply current figure 33-57. power-down supply current vs. temperature. figure 33-58. power-down supply current vs. temperature. with wdt and sampled bod enabled . 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a] 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a]
203 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.4 power-save supply current figure 33-59. power-save supply current vs. temperature. with wdt, sampled bod, and rtc from ulp enabled . 33.2.5 pin pull-up figure 33-60. reset pull-up resist or current vs. reset pin voltage. v cc = 1.8v . 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] i cc [a] 85c 25c -40c 0 20 40 60 80 100 v reset [v] i reset [a] 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
204 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-61. reset pull-up resist or current vs. reset pin voltage. v cc = 3.0v . figure 33-62. reset pull-up resist or current vs. reset pin voltage. v cc = 3.3v . 85c 25c -40c 0 20 40 60 80 100 120 140 160 v reset [v] i reset [a] 0 0.5 1.0 1.5 2.0 2.5 3.0 85c 25c -40c 0 20 40 60 80 100 120 140 160 180 v reset [v] i reset [a] 0 0.5 1.0 1.5 2.0 2.5 3.0
205 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.6 pin output voltage vs. sink/source current figure 33-63. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-64. i/o pin output voltage vs. source current. v cc = 3.0v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i pin [ma] v pin [v] -6 -5 -4 -3 -2 -1 0 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i pin [ma] v pin [v] -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
206 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-65. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-66. i/o pin output voltage vs. sink current. v cc = 1.8v . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i pin [ma] v pin [v] -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i pin [ma] v pin [v] 25c 85c 0 1 2 3 4 5 6 7 8 9 10
207 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-67. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-68. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i pin [ma] v pin [v] 0 1 2 3 4 5 6 7 8 9 10 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i pin [ma] v pin [v] 0 1 2 3 4 5 6 7 8 9 10
208 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.7 thresholds and hysteresis figure 33-69. i/o pin input threshold voltage vs. v cc . v ih - i/o pin read as ?1? . figure 33-70. i/o pin input threshold voltage vs. v cc . v il - i/o pin read as ?0? . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
209 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-71. i/o pin input hysteresis vs. v cc . figure 33-72. reset input threshold voltage vs. v cc . v il - i/o pin read as ?1? . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
210 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-73. reset input threshold voltage vs. v cc . v il - i/o pin read as ?0? . 33.2.8 bod thresholds figure 33-74. bod thresholds vs. temperature. bod level = 1.6v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v cc [v] v threshold [v] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 rising vcc falling vcc 1.61 1.62 1.63 1.64 1.65 1.66 1.67 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] v bot [v]
211 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-75. bod thresholds vs. temperature. bod level = 2.9v . 33.2.9 oscillators and wake-up time 33.2.9.1 internal 32.768khz oscillator figure 33-76. internal 32.768khz os cillator calibration step size. t = -40 to 85c, v cc = 3v . rising vcc falling vcc 2.90 2.92 2.94 2.96 2.98 3.00 3.02 3.04 3.06 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] v bot [v] 0 32 64 96 128 160 192 224 256 rc32kcal[7..0] 0.05% 0.20% 0.35% 0.50% 0.65% 0.80% step size: f [khz]
212 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.9.2 internal 2mhz oscillator figure 33-77. internal 2mhz oscill ator cala calibration step size. t = -40 to 85c, v cc = 3v . figure 33-78. internal 2mhz oscill ator calb calibration step size. t = -40 to 85c, v cc = 3v . -0.30% -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 0.40% 0.50% 0 163248648096112128 dfllrc2mcala step size: f [mhz] 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 0 8 16 24 32 40 48 56 64 dfllrc2mcalb step size: f [mhz]
213 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.9.3 internal 32mhz oscillator figure 33-79. internal 32mhz oscillator cala calibration step size. t = -40 to 85c, v cc = 3v . figure 33-80. internal 32mhz oscillator calb calibration step size. t = -40 to 85c, v cc = 3v . -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 0.40% 0.50% 0.60% 0 163248648096112128 dfllrc32mcala step size: f [mhz] 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 0 8 16 24 32 40 48 56 64 dfllrc32mcalb step size: f [mhz]
214 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.10 module current consumption figure 33-81. ac current consumption vs. v cc . low-power mode . figure 33-82. power-up current consumption vs. v cc . 85c 25c -40c 0 20 40 60 80 100 120 v cc [v] module current consumption [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85c 25c -40c 0 100 200 300 400 500 600 700 v cc [v] i cc [a] 0.4 0.6 0.8 1.0 1.2 1.4 1.6
215 xmega d3 [datasheet] 8134m?avr?08/2013 33.2.11 reset pulse width figure 33-83. minimum reset pulse width vs. v cc . 33.2.12 pdi speed figure 33-84. pdi speed vs. v cc . 85c 25c -40c 0 20 40 60 80 100 120 v cc [v] t rst [ns] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 25c 0 5 10 15 20 25 30 35 v cc [v] f max [mhz] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
216 xmega d3 [datasheet] 8134m?avr?08/2013 33.3 atmel atxmega128d3 33.3.1 current consumption 33.3.1.1 active supply current figure 33-85. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-86. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 0 100 200 300 400 500 600 700 800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 icc [a] frequency [mhz] 3.6v 3.3v 3.0v 2.7v 0 2 4 6 8 10 12 0 4 8 121620242832 icc [ma] frequency [mhz] 1.8v 2.2v
217 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-87. active supply current vs. v cc . f sys = 32.768khz internal rc . figure 33-88. active supply current vs. v cc . f sys = 1.0mhz external clock . 85 c 25c -40c 0 50 100 150 200 250 300 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v] 85c 25c -40c 200 300 400 500 600 700 800 900 1000 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [a] v cc [v]
218 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-89. active supply current vs. v cc . f sys = 2.0mhz internal rc . figure 33-90. active supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz. 85c 25c -40c 0 200 400 600 800 1000 1200 1400 1600 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v] 85c 25c -40c 0 1 2 3 4 5 6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [ma] v cc [v]
219 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-91. active supply current vs. v cc . f sys = 32mhz internal rc . 33.3.1.2 idle supply current figure 33-92. idle supply current vs. frequency. f sys = 0 - 1.0mhz, t = 25c . 85c 25c -40c 4 5 6 7 8 9 10 11 12 13 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [ma] v cc [v] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 icc [a] frequency [mhz]
220 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-93. idle supply current vs. frequency. f sys = 1 - 32mhz, t = 25c . figure 33-94. idle supply current vs. v cc . f sys = 32.768khz internal rc . 3.6v 3.3v 3.0v 2.7v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 4 8 121620242832 icc [ma] frequency [mhz] 2.2v 1.8v 85 c 25c -40c 24 25 26 27 28 29 30 31 32 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v]
221 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-95. idle supply current vs. v cc . f sys = 1.0mhz external clock . figure 33-96. idle supply current vs. v cc . f sys = 2.0mhz internal rc . 85c 25 c -40 c 20 40 60 80 100 120 140 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v] 85 c 25c -40c 100 150 200 250 300 350 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v]
222 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-97. idle supply current vs. v cc . f sys = 32mhz internal rc prescaled to 8mhz . figure 33-98. idle supply current vs. v cc . f sys = 32mhz internal rc . 85c 25c -40c 400 600 800 1000 1200 1400 1600 1800 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v] 85c 25c -40c 2.5 3.0 3.5 4.0 4.5 5.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 icc [ma] v cc [v]
223 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.1.3 power-down supply current figure 33-99. power-down supply current vs. v cc . all functions disabled. figure 33-100. power-down supply current vs. v cc . watchdog and sampled bod enabled . 85c 25c -40c 0 0.5 1 1.5 2 2.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v] 85c 25c -4 0 c 0 0.5 1 1.5 2 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 icc [a] v cc [v]
224 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-101. power-down supply current vs. temperature. watchdog and sampled bod enabled and running from internal ulp oscillator . 33.3.2 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. 33.3.2.1 pull-up figure 33-102. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -45-35-25-15-5 5 1525354555657585 icc [a] temperature [ c] 3.3v 2.7v 1.8v 85c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i cc [a] v pin [v]
225 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-103. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . figure 33-104. i/o pin pull-up resistor current vs. input voltage. v cc = 3.3v . 85c 25c -40c 0 20 40 60 80 100 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 i cc [a] v pin [v] 85c 25c -40c 0 20 40 60 80 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 i cc [a] v pin [v]
226 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.2.2 output voltage vs . sink/source current figure 33-105. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-106. i/o pin output voltage vs. source current. v cc = 3.0v . 85 c 25 c - 40 c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 v pin [v] i pin [ma] 85 c 25 c - 40 c 0 0.5 1 1.5 2 2.5 3 3.5 -16 -14 -12 -10 -8 -6 -4 -2 0 v pin [v] i pin [ma]
227 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-107. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-108. i/o pin output voltage vs. sink current. v cc = 1.8v . 85 c 25 c - 40 c 0 0.5 1 1.5 2 2.5 3 3.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 v pin [v] i pin [ma] 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0123456789 v pin [v] i pin [ma]
228 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-109. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-110. i/o pin output voltage vs. sink current. v cc = 3.3v . 85 c 25c -40c 0 0.2 0.4 0.6 0.8 1 1.2 0246810121416 v pin [v] i pin [ma] 85c 25c -40c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 12 14 16 18 20 v pin [v] i pin [ma]
229 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.2.3 thresholds and hysteresis figure 33-111. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 33-112. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85c 25c -40c 0.8 1 1.2 1.4 1.6 1.8 2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vthreshold [v] v cc [v] 85c 25c -40c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vthreshold [v] v cc [v]
230 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-113. i/o pin input hysteresis vs. v cc . 33.3.3 adc characteristics figure 33-114. inl error vs. external v ref . t = 25c, v cc = 3.6v, external reference . 85c 25c -40c 0.15 0.175 0.2 0.225 0.25 0.275 0.3 0.325 0.35 0.375 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vthreshold [v] v cc [v] differential mode single-ended signed mode single-ended unsigned mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] inl[lsb]
231 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-115. inl error vs. sample rate. t = 25c, v cc = 3.6v , v ref = 3.0v external. figure 33-116. inl error vs. input code. differential mode single-ended signed mode single-ended unsigned mode 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 adc sample rate [ksps] inl[lsb] 50 100 150 200 250 300 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl[lsb]
232 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-117. dnl e rror vs. external v ref . t = 25c, v cc = 3.6v, external reference . figure 33-118. i/o pin input threshold voltage vs. v cc . t = 25c, v cc = 3.6v, v ref = 3.0v external . differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 50 100 150 200 250 300 adc sample rate [ksps] dnl [lsb]
233 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-119. dnl e rror vs. input code. figure 33-120. gain error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 1.01.21.41.61.82.02.22.42.62.83.0 v ref [v] gain error [mv]
234 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-121. gain error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps . figure 33-122. offset error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended unsigned mode -9 -8 -7 -6 -5 -4 -3 -2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] offset error [mv]
235 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-123. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 33-124. offset error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended unsigned mode -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -45-35-25-15-5 5 1525354555657585 temperature [c] gain error [mv] differential mode 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] offset error [mv]
236 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.4 analog comparator characteristics figure 33-125. analog comparator hysteresis vs. v cc . small hysteresis . figure 33-126. analog comparator hysteresis vs. v cc . large hysteresis . -40c 25c 85c 10 11 12 13 14 15 16 17 18 19 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] -40c 25c 85c 18 20 22 24 26 28 30 32 34 36 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
237 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-127. analog comparator current source vs. calibration value. v cc = 3.0v . figure 33-128. voltage scaler inl vs. scalefac. t = 25c, v cc = 3.0v . 85c 25c -40c 3 3.5 4 4.5 5 5.5 6 6.5 7 0123456789101112131415 i currentsource [a] currcaliba[3..0] 25c 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0 7 14 21 28 35 42 49 56 63 inl[lsb] scalefac
238 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.5 internal 1.0v reference characteristics figure 33-129. adc internal 1.0v reference vs. temperature. 33.3.6 bod characteristics figure 33-130. bod thresholds vs. temperature. bod level = 1.6v . 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 1.006 1.007 -45-35-25-15-5 5 1525354555657585 bandgap voltage [v] 3.6v 2.7v 1.6v temperature [ c] rising vcc falling vcc 1.582 1.584 1.586 1.588 1.59 1.592 1.594 1.596 -40-30-20-100 1020304050607080 v bot [v] temperature [c]
239 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-131. bod thresholds vs. temperature. bod level = 3.0v . 33.3.7 external reset characteristics figure 33-132. minimum re set pin pulse width vs. v cc . rising vcc falling vcc 2.98 2.99 3 3.01 3.02 3.03 3.04 3.05 0 1020304050607080 v bot [v] temperature [c] 85c 25c -40c 80 85 90 95 100 105 110 115 120 125 130 135 140 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 t rst [ns] v cc [v]
240 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-133. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v . figure 33-134. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i reset [a] v reset [v] 85c 25c -40c 0 20 40 60 80 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 i reset [a] v reset [v]
241 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-135. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v . figure 33-136. reset pin input threshold voltage vs. v cc . v ih - reset pin read as ?1? . 85c 25c -40c 0 20 40 60 80 100 120 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 i reset [a] v reset [v] -40 c 85c 25c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.61.8 2 2.22.42.62.8 3 3.23.43.6 v threshold [v] v cc [v]
242 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.8 oscillator characteristics 33.3.8.1 ultra low-powe r internal oscillator figure 33-137. ultra low-power internal oscillator frequency vs. temperature. 33.3.8.2 32.768khz internal oscillator figure 33-138. 32.768khz internal oscillator frequency vs. temperature. 3.6v 3.3v 3.0v 2.7v 1.8v 32 32.5 33 33.5 34 34.5 35 35.5 36 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 32.35 32.4 32.45 32.5 32.55 32.6 32.65 32.7 32.75 32.8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [khz] temperature [c]
243 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-139. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 33.3.8.3 2mhz internal oscillator figure 33-140. 2mhz internal oscillator frequency vs. temperature. dfll disabled . 3.0v 20 23 26 29 32 35 38 41 44 47 50 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 frequency [khz] rc32kcal[7..0] 3.3v 3.0v 2.7v 2.2v 1.8v 1.96 1.98 2 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [ c]
244 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-141. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.678khz internal oscillator . figure 33-142. 2mhz internal oscillator frequency vs. cala calibration value. v cc = 3.0v . 3.3v 3.0v 2.7v 2.2v 1.8v 1.97 1.975 1.98 1.985 1.99 1.995 2 2.005 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 85c 25c -40c 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 0 163248648096112128 frequecncy[mhz] cala
245 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.8.4 32mhz internal oscillator figure 33-143. 32mhz internal oscillator frequency vs. temperature. dfll disabled . figure 33-144. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.678khz internal oscillator . 3.3v 3.0v 2.7v 2.2v 1.8v 31.5 32 32.5 33 33.5 34 34.5 35 35.5 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [ c] 3.3v 3.0v 2.7v 2.2v 1.8v 31.6 31.65 31.7 31.75 31.8 31.85 31.9 31.95 32 32.05 32.1 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [mhz] temperature [c]
246 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-145. 32mhz internal oscillator cala calibration step value. v cc = 3.0v . figure 33-146. 32mhz internal oscillator frequency vs. calb calibration step value. v cc = 3.0v . 85c 25c -40c 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 step size [%] cala 85c 25c -40c 20 25 30 35 40 45 50 55 60 65 70 0 7 14 21 28 35 42 49 56 63 frequency [mhz] dfllrc32mcalb
247 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.8.5 32mhz internal oscillator calibrated to 48mhz figure 33-147. 48mhz internal oscillator frequency vs. temperature. dfll disabled . figure 33-148. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.678khz internal oscillator . 3.6v 3.3v 3.0v 2.7v 1.8v 47 48 49 50 51 52 53 54 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 3.6v 3.3v 3.0v 2.7v 1.8v 47.2 47.3 47.4 47.5 47.6 47.7 47.8 47.9 48 48.1 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c]
248 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.9 two-wire interface characteristics figure 33-149. sda hold time vs. temperature. figure 33-150. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -45-35-25-15-5 5 1525354555657585 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 v cc [v] hold time [ns] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
249 xmega d3 [datasheet] 8134m?avr?08/2013 33.3.10 pdi characteristics figure 33-151. maximum pdi frequency vs. v cc . 85c 25c -40c 7 9 11 13 15 17 19 21 23 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] f max [mhz]
250 xmega d3 [datasheet] 8134m?avr?08/2013 33.4 atmel atxmega192d3 33.4.1 current consumption 33.4.1.1 active mode supply current figure 33-152. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-153. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 0 50 100 150 200 250 300 350 400 450 500 550 600 650 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency [mhz] i cc [a] 3.3v 3.0v 2.7v 0 1 2 3 4 5 6 7 8 9 10 11 0 2 4 6 8 101214161820222426283032 frequency [mhz] i cc [ma] 2.2v 1.8v
251 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-154. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 33-155. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 30 60 90 120 150 180 210 240 270 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 200 250 300 350 400 450 500 550 600 650 700 750 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
252 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-156. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 33-157. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma]
253 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-158. active mode supply current vs. v cc . f sys = 32mhz internal oscillator . 33.4.1.2 idle mode supply current figure 33-159. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 7 8 9 10 11 12 13 14 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma] 3.3v 3.0v 2.7v 2.2v 1.8v 0 13 26 39 52 65 78 91 104 117 130 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency [mhz] i cc [a]
254 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-160. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 33-161. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.3v 3.0v 2.7v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 02468101214161820222426283032 frequency [mhz] i cc [ma] 2.2v 1.8v 85c 25c -40c 25 26 27 28 29 30 31 32 33 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
255 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-162. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 33-163. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 20 40 60 80 100 120 140 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 150 180 210 240 270 300 330 360 390 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
256 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-164. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 33-165. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85c 25c -40c 600 800 1000 1200 1400 1600 1800 2000 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma]
257 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.1.3 power-down mode supply current figure 33-166. power-down mode supply current vs. v cc . all functions disabled . figure 33-167. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
258 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-168. power-down mode supply current vs. temperature. watchdog and sampled bod enabled and running from internal ulp oscillator . 33.4.2 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. 33.4.2.1 pull-up figure 33-169. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -45-35-25-15-5 5 1525354555657585 temperature [c] i cc [a] 85c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v pin [v] i pin [a]
259 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-170. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . figure 33-171. i/o pin pull-up resistor current vs. input voltage. v cc = 3.3v . 0 12 24 36 48 60 72 84 96 108 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v pin [v] i pin [a] 85c 25c -40c 85c 25c -40c 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 v pin [v] i pin [a]
260 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.2.2 output voltage vs . sink/source current figure 33-172. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-173. i/o pin output voltage vs. source current. v cc = 3.0v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 i pin [ma] v pin [v] 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v]
261 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-174. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-175. i/o pin output voltage vs. sink current. v cc = 1.8v . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v] 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0123456789 i pin [ma] v pin [v] 85c
262 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-176. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-177. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 10121416 i pin [ma] v pin [v] -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 101214161820 i pin [ma] v pin [v] 85c 25c
263 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.2.3 thresholds and hysteresis figure 33-178. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 33-179. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85c 25c -40c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v]
264 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-180. i/o pin input hysteresis vs. v cc . 33.4.3 adc characteristics figure 33-181. inl error vs. external v ref . t = 25c, v cc = 3.6v, external reference . 85c 25c -40c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0.42 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] differential mode single-ended signed mode single-ended unsigned mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] inl[lsb]
265 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-182. inl error vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . figure 33-183. inl error vs. input code. differential mode single-ended signed mode single-ended unsigned mode 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 adc sample rate [ksps] inl[lsb] 50 100 150 200 250 300 -1.25 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 1.25 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl[lsb]
266 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-184. dnl e rror vs. external v ref . t = 25c, v cc = 3.6v, external reference . figure 33-185. dnl e rror vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 50 100 150 200 250 300 adc sample rate [ksps] dnl [lsb]
267 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-186. dnl e rror vs. input code. figure 33-187. gain error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 1.01.21.41.61.82.02.22.42.62.83.0 v ref [v] gain error [mv]
268 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-188. gain error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps . figure 33-189. offset error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended unsigned mode -9 -8 -7 -6 -5 -4 -3 -2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] offset error [mv]
269 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-190. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 33-191. offset error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps. differential mode single-ended signed mode single-ended unsigned mode -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -45-35-25-15-5 5 1525354555657585 temperature [c] gain error [mv] differential mode 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] offset error [mv]
270 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.4 analog comparator characteristics figure 33-192. analog comparator hysteresis vs. v cc . small hysteresis . figure 33-193. analog comparator hysteresis vs. v cc . large hysteresis . -40c 25c 85c 10 11 12 13 14 15 16 17 18 19 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv] -40c 25c 85c 18 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv]
271 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-194. analog comparator current source vs. calibration value. v cc = 3.0v. figure 33-195. voltage scaler inl vs. scalefac. t = 25c, v cc = 3.0v . 3.6v 3.0v 2.4v 2.0v 1.6v 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 calib[3..0] i [a] 25c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac inl [lsb]
272 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.5 internal 1.0v reference characteristics figure 33-196. adc internal 1.0v reference vs. temperature. 33.4.6 bod characteristics figure 33-197. bod thresholds vs. temperature. bod level = 1.6v . 3.0v 2.7v 1.8v 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 1.012 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] bandgap voltage [v] 1.612 1.614 1.616 1.618 1.620 1.622 1.624 1.626 -45-35-25-15-5 5 1525354555657585 temperature [c] v bot [v]
273 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-198. bod thresholds vs. temperature. bod level = 3.0v . 33.4.7 external reset characteristics figure 33-199. minimum re set pin pulse width vs. v cc . 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v] 85c 25c -40c 80 85 90 95 100 105 110 115 120 125 130 135 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] t rst [ns]
274 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-200. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v . figure 33-201. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v reset [v] i reset [a] 85c 25c -40c 0 13 26 39 52 65 78 91 104 117 130 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v reset [v] i reset [a]
275 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-202. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v . figure 33-203. reset pin input threshold voltage vs. v cc . v ih - reset pin read as ?1? . 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v reset [v] i reset [a] 85c 25c -40c 85c 25c -40c 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
276 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.8 oscillator characteristics 33.4.8.1 ultra low-power internal oscillator figure 33-204. ultra low-po wer internal oscillator frequency vs. temperature. 33.4.8.2 32.768khz internal oscillator figure 33-205. 32.768khz internal oscillator frequency vs. temperature. 31.0 31.5 32.0 32.5 33.0 33.5 34.0 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [khz] 3.6v 3.0v 2.7v 1.8v 32.30 32.35 32.40 32.45 32.50 32.55 32.60 32.65 32.70 32.75 32.80 32.85 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [khz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
277 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-206. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 33.4.8.3 2mhz internal oscillator figure 33-207. 2mhz internal oscillator frequency vs. temperature. dfll disabled . 3.0v 20 23 26 29 32 35 38 41 44 47 50 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 rc32kcal[7..0] frequency [khz] 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
278 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-208. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 33-209. 2mhz internal oscillator frequency vs. cala calibration value. v cc = 3v . 1.970 1.975 1.980 1.985 1.990 1.995 2.000 2.005 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 85c 25c -40c 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala frequency [mhz]
279 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.8.4 32mhz internal oscillator figure 33-210. 32mhz internal oscillator frequency vs. temperature. dfll disabled . figure 33-211. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 31.55 31.60 31.65 31.70 31.75 31.80 31.85 31.90 31.95 32.00 32.05 32.10 -45-35-25-15-5 5 1525354555657585 3.3v 3.0v 2.7v 2.2v 1.8v frequency [mhz] temperature [c]
280 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-212. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . figure 33-213. 32mhz internal oscillato r frequency vs. calb calibration value. v cc = 3.0v . 85c 25c -40c 0.10 0.13 0.16 0.19 0.22 0.25 0.28 0.31 0.34 0.37 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%] 85c 25c -40c 20 25 30 35 40 45 50 55 60 65 70 0 7 14 21 28 35 42 49 56 63 calb frequency [mhz]
281 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.8.5 32mhz internal oscillator calibrated to 48mhz figure 33-214. 48mhz internal oscillator frequency vs. temperature. dfll disabled. figure 33-215. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 47 48 49 50 51 52 53 54 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 47.3 47.4 47.5 47.6 47.7 47.8 47.9 48.0 48.1 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
282 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.9 two-wire interface characteristics figure 33-216. sda hold time vs. temperature. figure 33-217. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -45-35-25-15-5 5 1525354555657585 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 v cc [v] hold time [ns] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
283 xmega d3 [datasheet] 8134m?avr?08/2013 33.4.10 pdi characteristics figure 33-218. maximum pdi frequency vs. v cc . 85c 25c -40c 7 9 11 13 15 17 19 21 23 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] f max [mhz]
284 xmega d3 [datasheet] 8134m?avr?08/2013 33.5 atmel atxmega256d3 33.5.1 current consumption 33.5.1.1 active mode supply current figure 33-219. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-220. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 0 50 100 150 200 250 300 350 400 450 500 550 600 650 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency [mhz] i cc [a] 3.3v 3.0v 2.7v 0 1 2 3 4 5 6 7 8 9 10 11 0 2 4 6 8 101214161820222426283032 frequency [mhz] i cc [ma] 2.2v 1.8v
285 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-221. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 33-222. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 30 60 90 120 150 180 210 240 270 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 200 250 300 350 400 450 500 550 600 650 700 750 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
286 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-223. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 33-224. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma]
287 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-225. active mode supply current vs. v cc . f sys = 32mhz internal oscillator . 33.5.1.2 idle mode supply current figure 33-226. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 7 8 9 10 11 12 13 14 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma] 3.3v 3.0v 2.7v 2.2v 1.8v 0 13 26 39 52 65 78 91 104 117 130 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency [mhz] i cc [a]
288 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-227. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 33-228. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.3v 3.0v 2.7v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 02468101214161820222426283032 frequency [mhz] i cc [ma] 2.2v 1.8v 85c 25c -40c 25 26 27 28 29 30 31 32 33 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
289 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-229. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 33-230. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 20 40 60 80 100 120 140 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 150 180 210 240 270 300 330 360 390 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
290 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-231. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 33-232. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85c 25c -40c 600 800 1000 1200 1400 1600 1800 2000 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma]
291 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.1.3 power-down mode supply current figure 33-233. power-down mode supply current vs. v cc . all functions disabled . figure 33-234. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
292 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-235. power-down mode supply current vs. temperature. watchdog and sampled bod enabled and running from internal ulp oscillator . 33.5.2 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. 33.5.2.1 pull-up figure 33-236. i/o pin pull-up r esistor current vs. input voltage. v cc = 1.8v . 3.0v 2.7v 2.2v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -45-35-25-15-5 5 1525354555657585 temperature [c] i cc [a] 85c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v pin [v] i pin [a]
293 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-237. i/o pin pull-up r esistor current vs. input voltage. v cc = 3.0v . figure 33-238. i/o pin pull-up r esistor current vs. input voltage. v cc = 3.3v . 0 12 24 36 48 60 72 84 96 108 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v pin [v] i pin [a] 85c 25c -40c 85c 25c -40c 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 v pin [v] i pin [a]
294 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.2.2 output voltage vs . sink/source current figure 33-239. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-240. i/o pin output voltage vs. source current. v cc = 3.0v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 i pin [ma] v pin [v] 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v]
295 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-241. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-242. i/o pin output voltage vs. sink current. v cc = 1.8v . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v] 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0123456789 i pin [ma] v pin [v] 85c
296 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-243. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-244. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 10121416 i pin [ma] v pin [v] -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 101214161820 i pin [ma] v pin [v] 85c 25c
297 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.2.3 thresholds and hysteresis figure 33-245. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 33-246. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85c 25c -40c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v]
298 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-247. i/o pin input hysteresis vs. v cc . 33.5.3 adc characteristics figure 33-248. inl error vs. external v ref . t = 25c, v cc = 3.6v, external reference . 85c 25c -40c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0.42 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] differential mode single-ended signed mode single-ended unsigned mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] inl[lsb]
299 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-249. inl error vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . figure 33-250. inl error vs. input code. differential mode single-ended signed mode single-ended unsigned mode 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 adc sample rate [ksps] inl[lsb] 50 100 150 200 250 300 -1.25 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 1.25 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl[lsb]
300 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-251. dnl e rror vs. external v ref . t = 25c, v cc = 3.6v, external reference . figure 33-252. dnl e rror vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 50 100 150 200 250 300 adc sample rate [ksps] dnl [lsb]
301 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-253. dnl e rror vs. input code. figure 33-254. gain error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 1.01.21.41.61.82.02.22.42.62.83.0 v ref [v] gain error [mv]
302 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-255. gain error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps . figure 33-256. offset error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended unsigned mode -9 -8 -7 -6 -5 -4 -3 -2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] offset error [mv]
303 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-257. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 33-258. offset error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps. differential mode single-ended signed mode single-ended unsigned mode -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -45-35-25-15-5 5 1525354555657585 temperature [c] gain error [mv] differential mode 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] offset error [mv]
304 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.4 analog comparator characteristics figure 33-259. analog comparator hysteresis vs. v cc . small hysteresis . figure 33-260. analog comparator hysteresis vs. v cc . large hysteresis . -40c 25c 85c 10 11 12 13 14 15 16 17 18 19 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv] -40c 25c 85c 18 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv]
305 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-261. analog comparator current source vs. calibration value. v cc = 3.0v. figure 33-262. voltage scaler inl vs. scalefac. t = 25c, v cc = 3.0v . 3.6v 3.0v 2.4v 2.0v 1.6v 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 calib[3..0] i [a] 25c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac inl [lsb]
306 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.5 internal 1.0v reference characteristics figure 33-263. adc internal 1.0v reference vs. temperature. 33.5.6 bod characteristics figure 33-264. bod thresholds vs. temperature. bod level = 1.6v . 3.0v 2.7v 1.8v 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 1.012 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] bandgap voltage [v] 1.612 1.614 1.616 1.618 1.620 1.622 1.624 1.626 -45-35-25-15-5 5 1525354555657585 temperature [c] v bot [v]
307 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-265. bod thresholds vs. temperature. bod level = 3.0v . 33.5.7 external reset characteristics figure 33-266. minimum re set pin pulse width vs. v cc . 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v] 85c 25c -40c 80 85 90 95 100 105 110 115 120 125 130 135 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] t rst [ns]
308 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-267. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v . figure 33-268. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v reset [v] i reset [a] 85c 25c -40c 0 13 26 39 52 65 78 91 104 117 130 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v reset [v] i reset [a]
309 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-269. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v . figure 33-270. reset pin input threshold voltage vs. v cc . v ih - reset pin read as ?1? . 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v reset [v] i reset [a] 85c 25c -40c 85c 25c -40c 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
310 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.8 oscillator characteristics 33.5.8.1 ultra low-power internal oscillator figure 33-271. ultra low-po wer internal oscillator frequency vs. temperature. 33.5.8.2 32.768khz internal oscillator figure 33-272. 32.768khz internal oscillator frequency vs. temperature. 31.0 31.5 32.0 32.5 33.0 33.5 34.0 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [khz] 3.6v 3.0v 2.7v 1.8v 32.30 32.35 32.40 32.45 32.50 32.55 32.60 32.65 32.70 32.75 32.80 32.85 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [khz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
311 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-273. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 33.5.8.3 2mhz internal oscillator figure 33-274. 2mhz internal oscillator frequency vs. temperature. dfll disabled . 3.0v 20 23 26 29 32 35 38 41 44 47 50 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 rc32kcal[7..0] frequency [khz] 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
312 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-275. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 33-276. 2mhz internal oscillator frequency vs. cala calibration value. v cc = 3v . 1.970 1.975 1.980 1.985 1.990 1.995 2.000 2.005 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 85c 25c -40c 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala frequency [mhz]
313 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.8.4 32mhz internal oscillator figure 33-277. 32mhz internal oscillator frequency vs. temperature. dfll disabled . figure 33-278. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 31.55 31.60 31.65 31.70 31.75 31.80 31.85 31.90 31.95 32.00 32.05 32.10 -45-35-25-15-5 5 1525354555657585 3.3v 3.0v 2.7v 2.2v 1.8v frequency [mhz] temperature [c]
314 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-279. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . figure 33-280. 32mhz internal oscillato r frequency vs. calb calibration value. v cc = 3.0v . 85c 25c -40c 0.10 0.13 0.16 0.19 0.22 0.25 0.28 0.31 0.34 0.37 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%] 85c 25c -40c 20 25 30 35 40 45 50 55 60 65 70 0 7 14 21 28 35 42 49 56 63 calb frequency [mhz]
315 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.8.5 32mhz internal oscillator calibrated to 48mhz figure 33-281. 48mhz internal oscillator frequency vs. temperature. dfll disabled. figure 33-282. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 47 48 49 50 51 52 53 54 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v 47.3 47.4 47.5 47.6 47.7 47.8 47.9 48.0 48.1 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
316 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.9 two-wire interface characteristics figure 33-283. sda hold time vs. temperature. figure 33-284. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -45-35-25-15-5 5 1525354555657585 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 v cc [v] hold time [ns] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
317 xmega d3 [datasheet] 8134m?avr?08/2013 33.5.10 pdi characteristics figure 33-285. maximum pdi frequency vs. v cc . 85c 25c -40c 7 9 11 13 15 17 19 21 23 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] f max [mhz]
318 xmega d3 [datasheet] 8134m?avr?08/2013 33.6 atmel atxmega384d3 33.6.1 current consumption 33.6.1.1 active mode supply current figure 33-286. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 33-287. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 200 300 400 500 600 700 800 900 1000 1100 1200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] i cc [a] 3.6v 3.3v 3.0v 2.7v 0 2 4 6 8 10 12 14 0 2 4 6 8 101214161820222426283032 frequency[mhz] i cc [ma] 2.2v 1.8v
319 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-288. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 33-289. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 0 50 100 150 200 250 300 350 400 450 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 300 400 500 600 700 800 900 1000 1100 1200 1300 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] icc [a]
320 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-290. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 33-291. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 150 200 250 300 350 400 450 500 550 600 650 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma]
321 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-292. active mode supply current vs. v cc . f sys = 32mhz internal oscillator . 33.6.1.2 idle mode supply current figure 33-293. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 2 3 4 5 6 7 8 9 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] i cc [a]
322 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-294. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 33-295. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.6v 3.3v 3.0v 2.7v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 2 4 6 8 101214161820222426283032 frequency [mhz] i cc [ma] 2.2v 1.8v 85c 25c -40c 28 29 30 31 32 33 34 35 36 37 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] icc [a]
323 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-296. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 33-297. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 40 50 60 70 80 90 100 110 120 130 140 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 150 175 200 225 250 275 300 325 350 375 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
324 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-298. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 33-299. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85c 25c -40c 500 700 900 1100 1300 1500 1700 1900 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 5250 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [a]
325 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.1.3 power-down mode supply current figure 33-300. power-down mode supply current vs. v cc . all functions disabled . figure 33-301. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 0 1 2 3 4 5 6 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] icc [a]
326 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-302. power-down mode supply current vs. temperature. watchdog and sampled bod enabled and running from internal ulp oscillator . 33.6.2 i/o pin characteristics the i/o pins complies with the jede c lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. 33.6.2.1 pull-up figure 33-303. i/o pin pull-up r esistor current vs. input voltage. v cc = 1.8v . 0 1 2 3 4 5 6 7 -45-35-25-15-5 5 1525354555657585 temperature [c] icc [a] 3.0v 2.7v 2.2v 1.8v 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v pin [v] i pin [a] 85c 25c -40c
327 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-304. i/o pin pull-up r esistor current vs. input voltage. v cc = 3.0v . figure 33-305. i/o pin pull-up r esistor current vs. input voltage. v cc = 3.3v . 0 12 24 36 48 60 72 84 96 108 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v pin [v] i pin [a] 85c 25c -40c 85c 25c -40c 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v pin [v] i pin [a]
328 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.2.2 output voltage vs . sink/source current figure 33-306. i/o pin output voltage vs. source current. v cc = 1.8v . figure 33-307. i/o pin output voltage vs. source current. v cc = 3.0v . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 i pin [ma] v pin [v] 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v]
329 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-308. i/o pin output voltage vs. source current. v cc = 3.3v . figure 33-309. i/o pin output voltage vs. sink current. v cc = 1.8v . 85c 25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 i pin [ma] v pin [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0123456789 i pin [ma] v pin [v] 85c 25c -40c
330 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-310. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 33-311. i/o pin output voltage vs. sink current. v cc = 3.3v . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 10 12 14 16 i pin [ma] v pin [v] 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 101214161820 i pin [ma] v pin [v] 85c 25c -40c
331 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.2.3 thresholds and hysteresis figure 33-312. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 33-313. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85c 25c -40c 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v]
332 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-314. i/o pin input hysteresis vs. v cc . 33.6.3 adc characteristics figure 33-315. inl error vs. external v ref . t = 25c, v cc = 3.6v, external reference . 85c 25c -40c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0.42 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] vthreshold [v] differential mode single-ended signed mode single-ended unsigned mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] inl[lsb]
333 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-316. inl error vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . figure 33-317. inl error vs. input code. differential mode single-ended signed mode single-ended unsigned mode 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 adc sample rate [ksps] inl[lsb] 50 100 150 200 250 300 -1.25 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 1.25 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl[lsb]
334 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-318. dnl e rror vs. external v ref . t = 25c, v cc = 3.6v, external reference . figure 33-319. dnl e rror vs. sample rate. t = 25c, v cc = 3.6v, v ref = 3.0v external . differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 50 100 150 200 250 300 adc sample rate [ksps] dnl [lsb]
335 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-320. dnl e rror vs. input code. figure 33-321. gain error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] differential mode single-ended signed mode single-ended unsigned mode -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 1.01.21.41.61.82.02.22.42.62.83.0 v ref [v] gain error [mv]
336 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-322. gain error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps . figure 33-323. offset error vs. v ref . t = 25c, v cc = 3.6v, adc sample rate = 300ksps . differential mode single-ended signed mode single-ended unsigned mode -9 -8 -7 -6 -5 -4 -3 -2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 v ref [v] offset error [mv]
337 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-324. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 33-325. offset error vs. v cc . t = 25c, v ref = external 1.0v, adc sample rate = 300ksps. differential mode single-ended signed mode single-ended unsigned mode -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -45-35-25-15-5 5 1525354555657585 temperature [c] gain error [mv] differential mode 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] offset error [mv]
338 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.4 analog comparator characteristics figure 33-326. analog comparator hysteresis vs. v cc . small hysteresis . figure 33-327. analog comparator hysteresis vs. v cc . large hysteresis . -40c 25c 85c 10 11 12 13 14 15 16 17 18 19 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv] -40c 25c 85c 18 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hyst [mv]
339 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-328. analog comparator current source vs. calibration value. v cc = 3.0v. figure 33-329. voltage scaler inl vs. scalefac. t = 25c, v cc = 3.0v . 2 3 4 5 6 7 8 0123456789101112131415 caliba[3..0] i [a] 3.6v 3.0v 2.4v 2.0v 1.6v 25c 0.20 0.23 0.26 0.29 0.32 0.35 0.38 0.41 0.44 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac inl [lsb]
340 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.5 internal 1.0v reference characteristics figure 33-330. adc internal 1.0v reference vs. temperature. 33.6.6 bod characteristics figure 33-331. bod thresholds vs. temperature. bod level = 1.6v . 3.6v 2.4v 1.6v 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 1.035 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] bandgap voltage [v] 1.50 1.54 1.58 1.62 1.66 1.70 1.74 1.78 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] vbot [v]
341 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-332. bod thresholds vs. temperature. bod level = 3.0v . 33.6.7 external reset characteristics figure 33-333. minimum re set pin pulse width vs. v cc . 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 -45-35-25-15-5 5 1525354555657585 temperature [c] vbot [v] 85c 25c -40c 80 85 90 95 100 105 110 115 120 125 130 135 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] t rst [ns]
342 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-334. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v . figure 33-335. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v reset [v] i reset [a] 85c 25c -40c 0 13 26 39 52 65 78 91 104 117 130 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v reset [v] i reset [a]
343 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-336. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v . figure 33-337. reset pin input threshold voltage vs. v cc . v ih - reset pin read as ?1? . 0 14 28 42 56 70 84 98 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v reset [v] i reset [a] 85c 25c -40c 85c 25c -40c 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
344 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.8 oscillator characteristics 33.6.8.1 ultra low-power internal oscillator figure 33-338. ultra low-po wer internal oscillator frequency vs. temperature. 33.6.8.2 32.768khz internal oscillator figure 33-339. 32.768khz internal oscillator frequency vs. temperature. 32.0 32.5 33.0 33.0 34.0 34.5 35.0 35.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [khz] 3.6v 3.0v 2.7v 1.8v 32.51 32.54 32.57 32.60 32.63 32.66 32.69 32.72 32.75 32.78 32.81 32.84 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [khz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.6v
345 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-340. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 33.6.8.3 2mhz internal oscillator figure 33-341. 2mhz internal oscillator frequency vs. temperature. dfll disabled . 3.0v 23 26 29 32 35 38 41 44 47 50 53 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 rc32kcal[7..0] frequency [khz] 3.3v 3.0v 2.7v 2.2v 1.8v 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz]
346 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-342. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 33-343. 2mhz internal oscillator frequency vs. cala calibration value. v cc = 3v . 1.8v 2.2v 2.7v 3.0v 3.3v 1.988 1.990 1.992 1.994 1.996 1.998 2.000 2.002 2.004 2.006 2.008 2.010 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 85c 25c -40c 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala frequency [mhz]
347 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.8.4 32mhz internal oscillator figure 33-344. 32mhz internal oscillator frequency vs. temperature. dfll disabled . figure 33-345. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.3v 3.0v 2.7v 2.2v 1.8v 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 31.76 31.79 31.82 31.85 31.88 31.91 31.94 31.97 32.00 32.03 32.06 32.09 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz]
348 xmega d3 [datasheet] 8134m?avr?08/2013 figure 33-346. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . figure 33-347. 32mhz internal oscillato r frequency vs. calb calibration value. v cc = 3.0v . 85c 25c -40c 0.15 0.18 0.21 0.24 0.27 0.30 0.33 0.36 0.39 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size:[%] 85c 25c -40c 20 26 32 38 44 50 56 62 68 74 80 0 7 14 21 28 35 42 49 56 63 dfllrc2mcalb frequency [mhz]
349 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.8.5 32mhz internal oscillator calibrated to 48mhz figure 33-348. 48mhz internal oscillator frequency vs. temperature. dfll disabled. figure 33-349. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.3v 3.0v 2.7v 2.2v 1.8v 47 48 49 50 51 52 53 54 55 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 47.6 47.7 47.8 47.9 48.0 48.1 48.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz]
350 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.9 two-wire interface characteristics figure 33-350. sda hold time vs. temperature. figure 33-351. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -45-35-25-15-5 5 1525354555657585 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 v cc [v] hold time [ns] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
351 xmega d3 [datasheet] 8134m?avr?08/2013 33.6.10 pdi characteristics figure 33-352. maximum pdi frequency vs. v cc . 85c 25c -40c 11 16 21 26 31 36 v cc [v] f max [mhz] 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
352 xmega d3 [datasheet] 8134m?avr?08/2013 34. errata 34.1 atmel atxmega32d3 34.1.1 rev. i ? ac system status flags are only valid if ac-system is enabled ? temperature sensor not calibrated 1. ac system status flags are only valid if ac-system is enabled the status flags for the ac-output are updated even though the ac is not enabled which is invalid. also, it is not possible to clear the ac interrupt flags wit hout enabling either of the analog comparators. problem fix/workaround software should clear the ac system flags once, after enabl ing the ac system before using the ac system status flags. 2. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.1.2 rev a - h not sampled
353 xmega d3 [datasheet] 8134m?avr?08/2013 34.2 atmel atxmega64d3 34.2.1 rev. i ? ac system status flags are only valid if ac-system is enabled ? temperature sensor not calibrated 1. ac system status flags are only valid if ac-system is enabled the status flags for the ac-output are updated even though the ac is not enabled which is invalid. also, it is not possible to clear the ac interrupt flags wit hout enabling either of the analog comparators. problem fix/workaround software should clear the ac system flags once, after enabl ing the ac system before using the ac system status flags. 2. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.2.2 rev. h not sampled. 34.2.3 rev. g not sampled. 34.2.4 rev. f not sampled. 34.2.5 rev. e ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? v cc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when v cc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared
354 xmega d3 [datasheet] 8134m?avr?08/2013 ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one an alog comparator (ac) and then selected/deselected as input for another ac, the fi rst comparator will be affected for up to 1s and co uld potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously , configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit v cc voltage scaler in the a nalog comparators is non-linear. figure 34-1. analog comparator voltage scaler vs. scalefac. t = 25c. problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed. 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
355 xmega d3 [datasheet] 8134m?avr?08/2013 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
356 xmega d3 [datasheet] 8134m?avr?08/2013 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. table 34-1. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
357 xmega d3 [datasheet] 8134m?avr?08/2013 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 18. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value.
358 xmega d3 [datasheet] 8134m?avr?08/2013 19. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 20. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 21. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 22. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none.
359 xmega d3 [datasheet] 8134m?avr?08/2013 23. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuin g the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 24. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 25. non available functions and options the below function and options are not available. writ ing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writin g to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none
360 xmega d3 [datasheet] 8134m?avr?08/2013 26. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.2.6 rev. d not sampled. 34.2.7 rev. c not sampled. 34.2.8 rev. b ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when vcc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one anal og comparator (ac) and then selected/deselected as input for another ac, the first compar ator will be affe cted for up to 1s and coul d potentially give a wrong comparison result.
361 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround if the bandgap is required for both acs simultaneous ly, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit v cc voltage scaler in the analog comparators is non-linear. figure 34-2. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed. 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
362 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
363 xmega d3 [datasheet] 8134m?avr?08/2013 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. table 34-2. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
364 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be wr itten while reading eeprom or flas h, or while executing code in active mode. problem fix/workaround enter idle sleep mode within 2.5s (five 2mhz clock cycles and 80 32mhz clock cycles) after starting an eeprom or flash write operation. wa ke-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write o peration has started, and then enter idle sleep mode. 18. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see ?xoscs el[3:0]: crystal oscillato r selection? in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 19. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value. 20. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none.
365 xmega d3 [datasheet] 8134m?avr?08/2013 21. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 22. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 23. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none. 24. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif.
366 xmega d3 [datasheet] 8134m?avr?08/2013 25. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 26. non available functions and options the below function and options are not av ailable. writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register. ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none. 27. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none
367 xmega d3 [datasheet] 8134m?avr?08/2013 34.2.9 rev. a not sampled.
368 xmega d3 [datasheet] 8134m?avr?08/2013 34.3 atmel atxmega128d3 34.3.1 rev. j ? ac system status flags are only valid if ac-system is enabled ? temperature sensor not calibrated 1. ac system status flags are only valid if ac-system is enabled the status flags for the ac-output are updated even though the ac is not enabled which is invalid. also, it is not possible to clear the ac interrupt flags wit hout enabling either of the analog comparators. problem fix/workaround software should clear the ac system flags once, after enabl ing the ac system before using the ac system status flags. 2. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.3.2 rev. i not sampled. 34.3.3 rev. h not sampled. 34.3.4 rev. g not sampled. 34.3.5 rev. f not sampled. 34.3.6 rev. e ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? v cc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when v cc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written
369 xmega d3 [datasheet] 8134m?avr?08/2013 ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one an alog comparator (ac) and then selected/deselected as input for another ac, the fi rst comparator will be affected for up to 1s and co uld potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously , configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit v cc voltage scaler in the a nalog comparators is non-linear. figure 34-3. analog comparator voltage scaler vs. scalefac. t = 25c. problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
370 xmega d3 [datasheet] 8134m?avr?08/2013 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
371 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. table 34-3. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
372 xmega d3 [datasheet] 8134m?avr?08/2013 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 18. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value.
373 xmega d3 [datasheet] 8134m?avr?08/2013 19. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 20. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 21. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 22. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none.
374 xmega d3 [datasheet] 8134m?avr?08/2013 23. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuin g the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 24. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 25. non available functions and options the below function and options are not available. writ ing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writin g to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none.
375 xmega d3 [datasheet] 8134m?avr?08/2013 26. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.3.7 rev. d not sampled. 34.3.8 rev. c not sampled. 34.3.9 rev. b ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when vcc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one anal og comparator (ac) and then selected/deselected as input for another ac, the first compar ator will be affe cted for up to 1s and coul d potentially give a wrong comparison result.
376 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround if the bandgap is required for both acs simultaneous ly, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit v cc voltage scaler in the analog comparators is non-linear. figure 34-4. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
377 xmega d3 [datasheet] 8134m?avr?08/2013 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
378 xmega d3 [datasheet] 8134m?avr?08/2013 enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. table 34-4. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
379 xmega d3 [datasheet] 8134m?avr?08/2013 for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be wr itten while reading eeprom or flas h, or while executing code in active mode. problem fix/workaround enter idle sleep mode within 2.5s (five 2mhz clock cycles and 80 32mhz clock cycles) after starting an eeprom or flash write operation. wa ke-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write o peration has started, and then enter idle sleep mode. 18. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 19. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value. 20. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none.
380 xmega d3 [datasheet] 8134m?avr?08/2013 21. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 22. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 23. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none. 24. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif.
381 xmega d3 [datasheet] 8134m?avr?08/2013 25. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 26. non available functions and options the below function and options are not av ailable. writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register. ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none. 27. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none
382 xmega d3 [datasheet] 8134m?avr?08/2013 34.3.10 rev. a not sampled.
383 xmega d3 [datasheet] 8134m?avr?08/2013 34.4 atmel atxmega192d3 34.4.1 rev. i ? ac system status flags are only valid if ac-system is enabled ? temperature sensor not calibrated 1. ac system status flags are only valid if ac-system is enabled the status flags for the ac-output are updated even though the ac is not enabled which is invalid. also, it is not possible to clear the ac interrupt flags wit hout enabling either of the analog comparators. problem fix/workaround software should clear the ac system flags once, after enabl ing the ac system before using the ac system status flags. 2. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.4.2 rev. h not sampled. 34.4.3 rev. g not sampled. 34.4.4 rev. f not sampled. 34.4.5 rev. e ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? v cc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when v cc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared
384 xmega d3 [datasheet] 8134m?avr?08/2013 ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one an alog comparator (ac) and then selected/deselected as input for another ac, the fi rst comparator will be affected for up to 1s and co uld potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously , configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear. figure 34-5. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3. adc gain stage cannot be used for single conversion 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
385 xmega d3 [datasheet] 8134m?avr?08/2013 the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
386 xmega d3 [datasheet] 8134m?avr?08/2013 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. table 34-5. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
387 xmega d3 [datasheet] 8134m?avr?08/2013 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 18. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value.
388 xmega d3 [datasheet] 8134m?avr?08/2013 19. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 20. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 21. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 22. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none.
389 xmega d3 [datasheet] 8134m?avr?08/2013 23. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuin g the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 24. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 25. non available functions and options the below function and options are not available. writ ing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writin g to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none.
390 xmega d3 [datasheet] 8134m?avr?08/2013 26. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.4.6 rev. d not sampled. 34.4.7 rev. c not sampled. 34.4.8 rev. b ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when vcc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one anal og comparator (ac) and then selected/deselected as input for another ac, the first compar ator will be affe cted for up to 1s and coul d potentially give a wrong comparison result.
391 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround if the bandgap is required for both acs simultaneous ly, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear. figure 34-6. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
392 xmega d3 [datasheet] 8134m?avr?08/2013 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
393 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. table 34-6. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
394 xmega d3 [datasheet] 8134m?avr?08/2013 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be wr itten while reading eeprom or flas h, or while executing code in active mode. problem fix/workaround enter idle sleep mode within 2.5s (five 2mhz clock cycles and 80 32mhz clock cycles) after starting an eeprom or flash write operation. wa ke-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write o peration has started, and then enter idle sleep mode. 18. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 19. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value. 20. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 21. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt.
395 xmega d3 [datasheet] 8134m?avr?08/2013 22. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 23. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none. 24. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 25. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction.
396 xmega d3 [datasheet] 8134m?avr?08/2013 26. non available functions and options the below function and options are not av ailable. writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register. ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none. 27. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.4.9 rev. a not sampled.
397 xmega d3 [datasheet] 8134m?avr?08/2013 34.5 atmel atxmega256d3 34.5.1 rev. i ? ac system status flags are only valid if ac-system is enabled ? temperature sensor not calibrated 1. ac system status flags are only valid if ac-system is enabled the status flags for the ac-output are updated even though the ac is not enabled which is invalid. also, it is not possible to clear the ac interrupt flags wit hout enabling either of the analog comparators. problem fix/workaround software should clear the ac system flags once, after enabl ing the ac system before using the ac system status flags. 2. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.5.2 rev. h not sampled. 34.5.3 rev. g not sampled. 34.5.4 rev. f not sampled. 34.5.5 rev. e ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? v cc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when v cc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared
398 xmega d3 [datasheet] 8134m?avr?08/2013 ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one an alog comparator (ac) and then selected/deselected as input for another ac, the fi rst comparator will be affected for up to 1s and co uld potentially give a wrong comparison result. problem fix/workaround if the bandgap is required for both acs simultaneously , configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear. figure 34-7. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
399 xmega d3 [datasheet] 8134m?avr?08/2013 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
400 xmega d3 [datasheet] 8134m?avr?08/2013 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generation mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. table 34-7. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
401 xmega d3 [datasheet] 8134m?avr?08/2013 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 18. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle after wake-up. the value read will be the same as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value.
402 xmega d3 [datasheet] 8134m?avr?08/2013 19. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 20. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt. 21. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 22. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none.
403 xmega d3 [datasheet] 8134m?avr?08/2013 23. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuin g the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 24. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction. 25. non available functions and options the below function and options are not available. writ ing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writin g to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none.
404 xmega d3 [datasheet] 8134m?avr?08/2013 26. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.5.6 rev. d not sampled. 34.5.7 rev. c not sampled. 34.5.8 rev. b ? bandgap voltage input for the acs can not be changed when used for both acs simultaneously ? vcc voltage scaler for ac is non-linear ? adc gain stage cannot be used for single conversion ? adc has increased inl error for some operating conditions ? adc gain stage output range is limited to 2.4v ? adc event on compare match non-functional ? adc propagation delay is not correct when 8 ? 64 gain is used ? bandgap measurement with the adc is non-functional when vcc is below 2.7v ? accuracy lost on first three samples after switching input to adc gain stage ? configuration of pgm and cwcm not as described in the xmega d manual ? pwm is not restarted properly after a fault in cycle-by-cycle mode ? bod will be enabled at any reset ? eeprom page buffer always written when nvm data0 is written ? pending full asynchronous pin change interrupts will not wake the device ? pin configuration does not affect analog comparator output ? nmi flag for crystal oscillator failure automatically cleared ? writing eeprom or flash while reading any of them will not work ? crystal start-up time required after power-s ave even if crystal is source for rtc ? rtc counter value not correctly read after sleep ? pending asynchronous rtc-interrupts will not wake up device ? twi transmit collision flag not cleared on repeated start ? clearing twi stop interrupt flag may lock the bus ? twi start condition at bus timeout will cause transaction to be dropped ? twi data interrupt flag (dif) erroneously read as set ? wdr instruction inside closed window will not issue reset ? non available functions and options ? temperature sensor not calibrated 1. bandgap voltage input for the acs cannot be changed when used for both acs simultaneously if the bandgap voltage is selected as input for one anal og comparator (ac) and then selected/deselected as input for another ac, the first compar ator will be affe cted for up to 1s and coul d potentially give a wrong comparison result.
405 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround if the bandgap is required for both acs simultaneous ly, configure the input selection for both acs before enabling any of them. 2. vcc voltage scaler for ac is non-linear the 6-bit vcc voltage scaler in the analog comparators is non-linear. figure 34-8. analog comparator voltage scaler vs. scalefac. t = 25c . problem fix/workaround use external voltage input for the analog comp arator if accurate voltage levels are needed 3. adc gain stage cannot be used for single conversion the adc gain stage will not output corr ect result for single conversion that is triggered and st arted from soft- ware or event system. problem fix/workaround when the gain stage is used, the adc must be set in free running mode for correct results. 4. adc has increased inl error for some operating conditions some adc configurations or operating condition will resu lt in increased inl error. in signed mode inl is increased to: 6lsb for sample rates above 130ksps, and up to 8lsb for 200ksps sample rate. 6lsb for reference voltage below 1.1v when v cc is above 3.0v. 20lsb for ambient temperature below 0c and reference voltage below 1.3v. in unsigned mode, the inl error cannot be gu aranteed, and this mode should not be used. problem fix/workaround none, avoid using the adc in the above configurations in order to prevent increased inl error. use the adc in signed mode also for single ended measurements. 3.3v 2.7v 1.8v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 scalefac v scale [v]
406 xmega d3 [datasheet] 8134m?avr?08/2013 5. adc gain stage output range is limited to 2.4v the amplified ou tput of the adc gain stage w ill never go above 2.4v, hence th e differential input will only give correct output when below 2.4v/gain. for the avail able gain settings, this gives a differential input range of: problem fix/workaround keep the amplified voltage output from the adc gain st age below 2.4v in order to get a correct result, or keep adc voltage reference below 2.4v. 6. adc event on compare match non-functional adc signalling event will be gi ven at every conversion co mplete even if interrupt mode (intmode) is set to below or above. problem fix/workaround enable and use interrupt on compare ma tch when using the compare function. 7. adc propagation delay is not correct when 8 ? 64 gain is used the propagation delay will increase by only one adc clock cycle for all gain settings. problem fix/workaround none. 8. bandgap measurement with the adc is non-functional when v cc is below 2.7v the adc can not be used to do bandgap measurements when v cc is below 2.7v. problem fix/workaround none. 9. accuracy lost on first three samples after switching input to adc gain stage due to memory effect in the adc gain stage, the firs t three samples after changing input channel must be disregarded to achieve 12-bit accuracy. problem fix/workaround run three adc conversions and discard these result s after changing input channels to adc gain stage. 10. configuration of pgm and cwcm not as described in xmega d manual enabling common waveform channel mode will enable pattern generat ion mode (pgm), but not common waveform channel mode. enabling pattern generation mode (pgm) and not common waveform channel mode (c wcm) will enable both pattern generation mode and common waveform channel mode. ? 1 gain: 2.4 v ? 2 gain: 1.2 v ? 4 gain: 0.6 v ? 8 gain: 300 mv ? 16 gain: 150 mv ? 32 gain: 75 mv ? 64 gain: 38 mv
407 xmega d3 [datasheet] 8134m?avr?08/2013 problem fix/workaround 11. pwm is not restarted properly after a fault in cycle-by-cycle mode when the awex fault restor e mode is set to cycle-by-cycle, the wa veform output will not return to normal operation at first update after fault condition is no longer present. problem fix/workaround do a write to any awex i/o register to re-enable the output. 12. bod will be enabled after any reset if any reset source goes acti ve, the bod will be enabled and keep the device in reset if the v cc voltage is below the programmed bod level. during power- on reset, reset will not be released until v cc is above the programmed bod level even if the bod is disabled. problem fix/workaround do not set the bod level higher than v cc even if the bod is not used. 13. eeprom page buffer always wr itten when nvm data0 is written if the eeprom is memory mapped, writing to nvm data0 will corrupt data in the eeprom page buffer. problem fix/workaround before writing to nvm data 0, for example when doing software crc or flash page buffer write, check if eeprom page buffer active loading flag (eeload) is set. do no t write nvm data0 w hen eeload is set. 14. pending full asynchronous pin change interrupts will not wake the device any full asynchronous pin-change interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the de vice is woken from another source or the source trigge rs again. this applies when entering all sleep modes where the system clock is stopped. problem fix/workaround none. 15. pin configuration does not affect analog comparator output the output/pull and inverted pin configuration does not affect the analog comparator output. problem fix/workaround none for output/pull configuration. for inverted i/o, configure the analog comparator to give an inverted result (that is, connect positive input to the negative ac input and vice versa), or use and exte rnal inverter to change polarity of analog comparator output. table 34-8. configure pwm and cwcm according to this table: pgm cwcm description 0 0 pgm and cwcm disabled 0 1 pgm enabled 1 0 pgm and cwcm enabled 1 1 pgm enabled
408 xmega d3 [datasheet] 8134m?avr?08/2013 16. nmi flag for crystal oscillator failure automatically cleared nmi flag for crystal oscillator failu re (xoscfdif) will be automatically cleared when executing the nmi interrupt handler. problem fix/workaround this device revision has only one nmi interrupt source, so checking the interrupt so urce in software is not required. 17. writing eeprom or flash while r eading any of them will not work the eeprom and flash cannot be wr itten while reading eeprom or flas h, or while executing code in active mode. problem fix/workaround enter idle sleep mode within 2.5s (five 2mhz clock cycles and 80 32mhz clock cycles) after starting an eeprom or flash write operation. wa ke-up source must either be eeprom ready or nvm ready interrupt. alternatively set up a timer/counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write o peration has started, and then enter idle sleep mode. 18. crystal start-up time required after power-save even if crystal is source for rtc even if 32.768khz crystal is used for rtc during slee p, the clock from the cryst al will not be ready for the system before the specified start-up time. see "xos csel[3:0]: crystal oscillato r selection" in xmega d manual. if bod is used in active mode, th e bod will be on during this period (0.5s). problem fix/workaround if faster start-up is required, go to slee p with internal oscillator as system clock. 19. rtc counter value not correctly read after sleep if the rtc is set to wake up the de vice on rtc overflow and bit 0 of rt c cnt is identical to bit 0 of rtc per as the device is entering sleep, the value in the rtc count register can not be read correctly within the first prescaled rtc clock cycle afte r wakeup. the value read will be the sa me as the value in the register when entering sleep. the same applies if rtc compare ma tch is used as wake-up source. problem fix/workaround wait at least one prescaled rtc clock cycle before reading the rtc cnt value. 20. pending asynchronous rtc-interrupts will not wake up device asynchronous interrupts from the real-time-counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. problem fix/workaround none. 21. twi transmit collision flag not cleared on repeated start the twi transmit collision flag shou ld be automatically cleared on start and repeated start, but is only cleared on start. problem fix/workaround clear the flag in software after address interrupt.
409 xmega d3 [datasheet] 8134m?avr?08/2013 22. clearing twi stop interrupt flag may lock the bus if software clears the stop interrupt flag (apif) on the same peri pheral clock cycle as the hardware sets this flag due to a new address received, clkhold is not cleared and the scl line is not released. this will lock the bus. problem fix/workaround check if the bus state is idle. if this is the case, it is safe to clear apif. if the bus state is not idle, wait for the scl pin to be lo w before clearing apif. code: /* only clear the interrupt flag if within a "safe zone". */ while ( /* bus not idle: */ ((comms_twi.master.status & twi_master_busstate_gm) != twi_master_busstate_idle_gc)) && /* scl not held by slave: */ !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* ensure that the scl line is low */ if ( !(comms_port.in & pin1_bm) ) if ( !(comms_port.in & pin1_bm) ) break; } /* check for an pending address match interrupt */ if ( !(comms_twi.slave.status & twi_slave_clkhold_bm) ) { /* safely clear interrupt flag */ comms_twi.slave.status |= (uint8_t)twi_slave_apif_bm; } 23. twi start condition at bus timeout will cause transaction to be dropped if bus timeout is enabled and a timeout occurs on th e same peripheral clock cycle as a start is detected, the transaction will be dropped. problem fix/workaround none. 24. twi data interrupt flag erroneously read as set when issuing the twi slave response command cmd=0b11, it takes one peripheral clock cycle to clear the data interrupt flag (dif). a read of dif directly after issuing the command will show the dif still set. problem fix/workaround add one nop instruction before checking dif. 25. wdr instruction inside closed window will not issue reset when a wdr instruction is execute within one ulp cloc k cycle after updating the window control register, the counter can be cleared without giving a system reset. problem fix/workaround wait at least one ulp clock cycle before executing a wdr instruction.
410 xmega d3 [datasheet] 8134m?avr?08/2013 26. non available functions and options the below function and options are not av ailable. writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location. ? twie, the twi module on porte ? twi sdahold option in the twi ctrl register is one bit ? crc generator module ? adc 1/2 gain option, and this configuration option in the gain bits in the adc channel ctrl register ? adc vcc/2 reference option and this configuration option in the refsel bits on the adc refctrl register ? adc option to use internal gnd as negative input in differential measurements and this configuration option in the muxneg bits in t he adc channel muxctrl register ? adc channel scan and the adc scan register ? adc current limitation option, and the currlimit bits in the adc ctrlb register ? adc impedance mode selection for the gain stage, and the impmode bit in the adc ctrlb register ? timer/counter 2 and the splitmode configuration opt ion in the bytem bits in the timer/counter 0 ctrle register ? analog comparator (ac) current output option, and the ac currctrl and currcalib registers ? port remap functions with alternate pin locations for timer/counter output compare channels, usart0 and spi, and the port remap register ? port rtc clock output option and the rtcout bit in the port clkevout register ? port remap functions with alternate pin locations for the clock and event output, and the clkevpin bit in the port clkevout register. ? tosc alternate pin locations, and toscsel bit in fusebyte2 ? real time counter clock source options of exte rnal clock from tosc1, and 32.768khz from tosc, and 32.768khz from the 32.768khz internal oscillator, and these configuration options in the rtcsrc bits in the clock rtctrl register ? pll divide by two option, and the plldiv bit in the clock pllctrl register ? pll lock detection failure function and the plldif and pllfden bits in the clock xoscfail register ? the high drive option for external crystal and the xoscpwr bit on the oscillator xoscctrl register ? the option to enable sequential startup of the analog modules and the anainit register in mcu control memory problem fix/workaround none. 27. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.5.9 rev. a not sampled.
411 xmega d3 [datasheet] 8134m?avr?08/2013 34.6 atmel atxmega384d3 34.6.1 rev. b ? temperature sensor not calibrated 1. temperature sensor not calibrated temperature sensor factory calibration not implemented. problem fix/workaround none 34.6.2 rev. a not sampled.
412 xmega d3 [datasheet] 8134m?avr?08/2013 35. datasheet revision history please note that the referring page numbers in this section ar e referred to this document. the referring revision in this section are referring to the document revision. 35.1 8134m ? 07/2013 35.2 8134l ? 07/2013 35.3 8134k ? 05/2013 35.4 8134j ? 03/2013 1. ?pinout/block diagram? on page 4 : usart0 removed from port f. 2. typical chara, figure 33-156 on page 252 and figure 33-323 on page 336 : scale on y-axis updated from ma to a. 1. added errata section for ?atmel atxmega32d3? on page 352 2. errata temperature sensor not calibrated added to: atxmega64d3 ?rev. i? , ?rev. e? and ?rev. b? . atxmega128d3 ?rev. j? , ?rev. e? and ?rev. b? . atxmega192d3 ?rev. i? , ?rev. e? and ?rev. b? . atxmega256d3 ?rev. i? , ?rev. e? and ?rev. b? . atxmega384d3 ?rev. b? . 1. ?errata? is updated. 1. almost all figures in chapter ?typical characteristics? are updated. 2. added new errata ?rev. g? on page 117. 3. added new errata ?rev. b? on page 125 and ?rev. e? on page 118. non available functions and options. 4. editing updates. 5. added atxmega32d3 and atxmega384d3. 6. new datasheet template is added. 7. a lot of small corrections and a complete reorganization of ?electrical characteristics? and ?typical characteristics? . 8. bullet ?optional slew rate control? in chapter ?i/o ports? on page 29 is removed 9. the sentence ?the port pins also have configurable slew rate limitation to reduce electromagnetic emission? in chapter ?i/o ports? on page 29 is removed.
413 xmega d3 [datasheet] 8134m?avr?08/2013 35.5 8134i ? 12/2010 10. the sentence ? the i/o pins complies with the jedec lvttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification? is added to section 32.1.5 on page 68 , section 32.2.5 on page 87 , section 32.6.5 on page 161 , section 33.3.2 on page 224 , section 33.4.2 on page 258 , section 33.5.2 on page 292 and section 33.6.2 on page 326 . 11. figure 2-1 on page 4 is updated by changing vdd to vcc. 12. table 7-1 on page 14 is updated. 13. figure 7-2 on page 15 is updated. 14. figure 14-7 on page 32 is updated. 15. former table 32-24, table 32-52, table 32-79, table 32-107 , table 32-135, table 32-163 (title: ?external clock?) have each been replaced by two new tables, named respectively ?external clock used as system clock without prescaling? and ?external clock with pr escaler for system clock?. 16. in table 32-29 on page 81 , table 32-57 on page 98 , table 32-86 on page 117 , table 32-115 on page 136 , table 32- 144 on page 155 , and table 32-172 on page 172 the value for the parameter ?input voltage? has been corrected. 17. in table 32-18 on page 73 , table 32-47 on page 92 , table 32-75 on page 109 , table 32-104 on page 128 , table 32- 133 on page 147 , and table 32-162 on page 166 the parameter ?application erase? has been added. 18. table 32-14 on page 72 , table 32-43 on page 91 , table 32-100 on page 127 , table 32-129 on page 146 and table 32-158 on page 165 (brownout detection characteristics) are updated. 19. table 32-20 on page 74 and table 32-49 on page 93 (2mhz internal oscillator characteristics) are updated. 20. table 32-21 on page 74 and table 32-50 on page 93 (32mhz internal oscillator characteristics) are updated. 21. accuracy added in table 32-108 on page 129 . 22. table 32-148 on page 158 has been corrected. 23 table 32-166 on page 167 ; ?factory calibration accuracy? and ?accuracy? is added. 24. table 32-149 on page 159 , table 32-151 on page 161 , table 32-153 on page 162 , table 32-154 on page 163 , table 32-155 on page 164 , and table 32-156 on page 164 has been updated. 25. section 1. ?ordering information? on page 2 is updated 26. former section 31.3 ?64z3? has been removed. 27. section 31.2 ?64m? on page 62 has replaced the former section 31.2 ?64m2?. 1. datasheet status changed to complete: preliminary removed from front page. 2. updated all tables in the the maximum cpu clock frequency depends on vcc. as shown in figure 32-8 on page 83 the frequency vs. vcc curve is linear between 1.8v < vcc < 2.7v. on page 64 3. replaced table 31-11 on page 67. 4. replaced table 31-17 on page 68 and added the figure ?tosc input capacitance? on page 78. 5. added ?rev. e? on page 118. 6. updated errata for adc (adc has increased inl error for some operating conditions). 7. updated errata ?rev. b? on page 125 with twie (twie is not available). 8. updated the last page by atmel new brand style guide.
414 xmega d3 [datasheet] 8134m?avr?08/2013 35.6 8134h ? 09/2010 35.7 8134g ? 08/2010 35.8 8134f ? 02/2010 35.9 8134e ? 01/2010 1. updated ?errata? on page 352 . 1. updated the footnote 3 of ?ordering information? on page 2 . 2. all references to crc removed. updated figure 3-1 on page 5. 3. updated ?features? on page 29 . 4. updated ?dc characteristics? on page 61 by adding icc for flash/eeprom programming. 5. added av cc in ?adc characteristics? on page 68. 6. updated start up time in ?adc characteristics? on page 68. 7. updated and fixed typo in ?errata? on page 352 . 1. added ?pdi speed? on page 105. 1. updated the device pin-out figure 2-1 on page 4 . pdi_clk and pdi_data renamed only pdi. 2. updated ?adc ? 12-bit analog to digital converter? on page 44 . 3. updated figure 25-1 on page 45 . 4. updated ?alternate pin function description? on page 49 . 5. updated ?alternate pin functions? on page 50 . 6. updated ?timer/counter and awex functions? on page 49 . 7. added table 31-17 on page 68. 8. added table 31-18 on page 69. 9. changed internal oscillator speed to ?power-on reset cu rrent consumption vs. vcc. bod level = 3.0v, enabled in continuous mode.? on page 108 10. updated ?errata? on page 352 .
415 xmega d3 [datasheet] 8134m?avr?08/2013 35.10 8134d ? 11/2009 35.11 8134c ? 10/2009 35.12 8134b ? 08/2009 35.13 8134a ? 03/2009 1. added table 31-3 on page 64, endurance and data retention 2. updated table 31-10 on page 67, input hysteresis is in v and not in mv. 3. added ?errata? on page 352 4. editing updates. 1. updated ?features? on page 1 with two-wire interfaces. 2. updated ?pinout/block diagram? on page 4 . 3. updated ?overview? on page 5 . 4. updated ?xmega d# block diagram? on page 5. 5. updated table 13-1 on page 28 . 6. updated ?overview? on page 38. 7. updated table 28-5 on page 53. 8. updated ?peripheral module address map? on page 54 . 1. added the maximum cpu clock frequency depends on vcc. as shown in figure 32-8 on page 83 the frequency vs. vcc curve is linear between 1.8v < vcc < 2.7v. on page 64 . 2. added ?typical characteristics? on page 174 . 1. initial revision.
416 xmega d3 [datasheet] 8134m?avr?08/2013
i xmega d3 [datasheet] 8134m?avr?08/2013 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. pinout/block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. avr cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 architectural overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 alu - arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 program flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.6 status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.7 stack and stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.8 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3 flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 fuses and lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 i/o memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 device id and revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10 i/o memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.11 flash and eeprom page size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. event system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9. system clock and clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . 22 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3 sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ii xmega d3 [datasheet] 8134m?avr?08/2013 11. system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.3 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.4 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12. wdt ? watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. interrupts and programmable multilevel interrupt controller . . . . . . . 27 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.3 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14. i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3 output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.4 input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.5 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15. tc0/1 ? 16-bit timer/counter type 0 and 1 . . . . . . . . . . . . . . . . . . 33 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 16. tc2 ? timer/counter type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17. awex ? advanced waveform extension . . . . . . . . . . . . . . . . . . . . . 36 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18. hi-res ? high resolution extension . . . . . . . . . . . . . . . . . . . . . . . . 37 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19. rtc ? 16-bit real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20. twi ? two-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21. spi ? serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 22. usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
iii xmega d3 [datasheet] 8134m?avr?08/2013 23. ircom ? ir communication module . . . . . . . . . . . . . . . . . . . . . . . . 42 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24. crc ? cyclic redundancy check generator . . . . . . . . . . . . . . . . . . 43 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 24.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 25. adc ? 12-bit analog to digital converter . . . . . . . . . . . . . . . . . . . . 44 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 26. ac ? analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 27. programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 27.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 27.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 28. pinout and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28.1 alternate pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28.2 alternate pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 29. peripheral module address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 30. instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 31. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 31.1 64a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 31.2 64m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 32. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32.1 atmel atxmega32d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32.2 atmel atxmega64d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 32.3 atmel atxmega128d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 32.4 atmel atxmega192d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 32.5 atmel atxmega256d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 32.6 atmel atxmega384d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 33. typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 33.1 atmel atxmega32d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 33.2 atmel atxmega64d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 33.3 atmel atxmega128d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 33.4 atmel atxmega192d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 33.5 atmel atxmega256d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 33.6 atmel atxmega384d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 34. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 34.1 atmel atxmega32d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 34.2 atmel atxmega64d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 34.3 atmel atxmega128d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 34.4 atmel atxmega192d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 34.5 atmel atxmega256d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
iv xmega d3 [datasheet] 8134m?avr?08/2013 34.6 atmel atxmega384d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 35. datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 35.1 8134m ? 08/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 35.2 8134l ? 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 35.3 8134k ? 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 35.4 8134j ? 03/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 35.5 8134i ? 12/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 35.6 8134h ? 09/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 35.7 8134g ? 08/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 35.8 8134f ? 02/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 35.9 8134e ? 01/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 35.10 8134d ? 11/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 35.11 8134c ? 10/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 35.12 8134b ? 08/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 35.13 8134a ? 03/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
v xmega d3 [datasheet] 8134m?avr?08/2013
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8134m?avr?08/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, adjacent key suppression ? , aks ? , avr ? , enabling unlimited possibilities ? , qtouch ? , xmega ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks o f others.

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